From patchwork Thu Apr 13 09:44:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126004 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8C3BD42931; Thu, 13 Apr 2023 11:50:24 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D841E42B7E; Thu, 13 Apr 2023 11:50:16 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 35F52410F9; Thu, 13 Apr 2023 11:50:14 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681379414; x=1712915414; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VQXRouaK+IKPG/RNj7a4FchRTe4L3XqOPsszmvYTy6E=; b=DrKBIJ1hT96lYNtLi0/+X9cL4r5QZz2j151PgEXJrZGspKlBE9FlkraI +NrV0TIREc42SQd1edg+nOdBpNcP4v5R15353OqpGM6+dyVAXpwuoPyD7 quIt8i9EWLoPuzR5uBPEHwsbolKD1S4f4/vQ3RA9f/eV3GR551+yilE+N kWl5mab9RpPpJWKh3/qGtQzehRdTfA/ro4Y4XdDC7MyxohxyElkgZjVi/ IFcd+hLGsN505+lTblOVCkHyqqrm/P84Xfom6mOPT9S0oNV3FaGh3hBBV 1/Whga1YhzgRpkou1CV+ualn6ATehNkIHD+Wd1cmHANHp01k/TJFzrtvK Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="409290359" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="409290359" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 02:50:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="778699245" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="778699245" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.119.244]) by FMSMGA003.fm.intel.com with ESMTP; 13 Apr 2023 02:50:10 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, Wenjing Qiao , stable@dpdk.org, Charles Stoll Subject: [PATCH 02/18] common/idpf: fix ctlq message send and receive Date: Thu, 13 Apr 2023 05:44:46 -0400 Message-Id: <20230413094502.1714755-3-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230413094502.1714755-1-wenjing.qiao@intel.com> References: <20230413094502.1714755-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fixes the ctlq send and receive functions to not cast the cookie field to a u64 before programming. By doing a cast, it can cause endianness issues as LE will swap the lower 32 and higher 32 bits whereas BE will not. By treating this field as two 32 bit values, both BE and LE will place the retval and opcode in the correct location. Since this field is now being treated as two 32 bit values, the cfg.data section must also be split into a data high and data low. Macros to easily pack and read these fields have also been added. Fixes: fb4ac04e9bfa ("common/idpf: introduce common library") Cc: stable@dpdk.org Signed-off-by: Charles Stoll Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/idpf_controlq.c | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/drivers/common/idpf/base/idpf_controlq.c b/drivers/common/idpf/base/idpf_controlq.c index 3af81e5a64..8e4d3ee54f 100644 --- a/drivers/common/idpf/base/idpf_controlq.c +++ b/drivers/common/idpf/base/idpf_controlq.c @@ -311,18 +311,14 @@ int idpf_ctlq_send(struct idpf_hw *hw, struct idpf_ctlq_info *cq, for (i = 0; i < num_q_msg; i++) { struct idpf_ctlq_msg *msg = &q_msg[i]; - u64 msg_cookie; desc = IDPF_CTLQ_DESC(cq, cq->next_to_use); desc->opcode = CPU_TO_LE16(msg->opcode); desc->pfid_vfid = CPU_TO_LE16(msg->func_id); - msg_cookie = *(u64 *)&msg->cookie; - desc->cookie_high = - CPU_TO_LE32(IDPF_HI_DWORD(msg_cookie)); - desc->cookie_low = - CPU_TO_LE32(IDPF_LO_DWORD(msg_cookie)); + desc->cookie_high = CPU_TO_LE32(msg->cookie.mbx.chnl_opcode); + desc->cookie_low = CPU_TO_LE32(msg->cookie.mbx.chnl_retval); desc->flags = CPU_TO_LE16((msg->host_id & IDPF_HOST_ID_MASK) << IDPF_CTLQ_FLAG_HOST_ID_S); @@ -620,8 +616,6 @@ int idpf_ctlq_recv(struct idpf_ctlq_info *cq, u16 *num_q_msg, num_to_clean = *num_q_msg; for (i = 0; i < num_to_clean; i++) { - u64 msg_cookie; - /* Fetch next descriptor and check if marked as done */ desc = IDPF_CTLQ_DESC(cq, ntc); flags = LE16_TO_CPU(desc->flags); @@ -639,10 +633,8 @@ int idpf_ctlq_recv(struct idpf_ctlq_info *cq, u16 *num_q_msg, if (flags & IDPF_CTLQ_FLAG_ERR) ret_code = -EBADMSG; - msg_cookie = (u64)LE32_TO_CPU(desc->cookie_high) << 32; - msg_cookie |= (u64)LE32_TO_CPU(desc->cookie_low); - idpf_memcpy(&q_msg[i].cookie, &msg_cookie, sizeof(u64), - IDPF_NONDMA_TO_NONDMA); + q_msg[i].cookie.mbx.chnl_opcode = LE32_TO_CPU(desc->cookie_high); + q_msg[i].cookie.mbx.chnl_retval = LE32_TO_CPU(desc->cookie_low); q_msg[i].opcode = LE16_TO_CPU(desc->opcode); q_msg[i].data_len = LE16_TO_CPU(desc->datalen);