From patchwork Fri Apr 14 03:51:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjun Wu X-Patchwork-Id: 126055 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 26D674293A; Fri, 14 Apr 2023 05:52:25 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2C3EB42D20; Fri, 14 Apr 2023 05:52:11 +0200 (CEST) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mails.dpdk.org (Postfix) with ESMTP id 5CA5740144; Fri, 14 Apr 2023 05:52:07 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681444326; x=1712980326; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9zc1e5iZNT/oSmzgnSg3O+aIopnp+SDV+IhPM1axGH4=; b=KjsjtkMBBoVnEFAqmcKXoRd+Id9Lb4SFjjT5QV/Fe8ipo9DS7ZlaH2y+ hn9jSs3sLVCZIqR1kfInEv57Ntprjdo9WJr5lG8XGpxVS2nRiCU2MC5OM fuwD9wbGdHywwr4owwurp9dCPV7q11Qgf5/fo4CALTwdYbYzxi0wPaZVU nXEudxfAsQ+hBz/yiUD+IgfRn2FaZtAZXqnpKawqZ5ZAZOZDMlL+pxghG MKvYgyzwEkJSKHnHc0sQZywQtAHSKx9q96BAQ5d60f0r4rhvpbmXXkwey Tqmwv63Upoz8uL82JLAoN6U5v0IKH1lmHq8gBPrG+Q90EjAh/hWuBJTvD w==; X-IronPort-AV: E=McAfee;i="6600,9927,10679"; a="343135756" X-IronPort-AV: E=Sophos;i="5.99,195,1677571200"; d="scan'208";a="343135756" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 20:52:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10679"; a="683192249" X-IronPort-AV: E=Sophos;i="5.99,195,1677571200"; d="scan'208";a="683192249" Received: from dpdk-wuwenjun-icelake-ii.sh.intel.com ([10.67.110.157]) by orsmga007.jf.intel.com with ESMTP; 13 Apr 2023 20:51:59 -0700 From: Wenjun Wu To: dev@dpdk.org, Yuying.Zhang@intel.com, beilei.xing@intel.com, jingjing.wu@intel.com, qiming.yang@intel.com, qi.z.zhang@intel.com Cc: Wenjun Wu , stable@dpdk.org Subject: [PATCH v1 2/5] net/ice: fix RX data buffer size Date: Fri, 14 Apr 2023 11:51:48 +0800 Message-Id: <20230414035151.1377726-3-wenjun1.wu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230414035151.1377726-1-wenjun1.wu@intel.com> References: <20230414035151.1377726-1-wenjun1.wu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch does two fixes. 1. No matter what the mbuf size is, the data buffer size should not be greater than 16K - 128. 2. Replace RTE_ALIGN with RTE_ALIGN_FLOOR according to [1]. [1] Commit c9c45beb1b97 ("net/iavf: fix Rx queue buffer size alignment") Fixes: 50370662b727 ("net/ice: support device and queue ops") Fixes: 1b009275e2c8 ("net/ice: add Rx queue init in DCF") Cc: stable@dpdk.org Signed-off-by: Wenjun Wu --- drivers/net/ice/ice_dcf_ethdev.c | 3 ++- drivers/net/ice/ice_rxtx.c | 3 ++- drivers/net/ice/ice_rxtx.h | 3 +++ 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/net/ice/ice_dcf_ethdev.c b/drivers/net/ice/ice_dcf_ethdev.c index dcbf2af5b0..7304ea721c 100644 --- a/drivers/net/ice/ice_dcf_ethdev.c +++ b/drivers/net/ice/ice_dcf_ethdev.c @@ -115,7 +115,8 @@ ice_dcf_init_rxq(struct rte_eth_dev *dev, struct ice_rx_queue *rxq) buf_size = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM; rxq->rx_hdr_len = 0; - rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S)); + rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size, (1 << ICE_RLAN_CTX_DBUF_S)); + rxq->rx_buf_len = RTE_MIN(rxq->rx_buf_len, ICE_RX_MAX_DATA_BUF_SIZE); max_pkt_len = RTE_MIN(ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len, dev->data->mtu + ICE_ETH_OVERHEAD); diff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c index 0ea0045836..560c1a4af7 100644 --- a/drivers/net/ice/ice_rxtx.c +++ b/drivers/net/ice/ice_rxtx.c @@ -259,7 +259,8 @@ ice_program_hw_rx_queue(struct ice_rx_queue *rxq) /* Set buffer size as the head split is disabled. */ buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM); - rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S)); + rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size, (1 << ICE_RLAN_CTX_DBUF_S)); + rxq->rx_buf_len = RTE_MIN(rxq->rx_buf_len, ICE_RX_MAX_DATA_BUF_SIZE); rxq->max_pkt_len = RTE_MIN((uint32_t)ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len, frame_size); diff --git a/drivers/net/ice/ice_rxtx.h b/drivers/net/ice/ice_rxtx.h index 94f6bcf3d1..89569029e1 100644 --- a/drivers/net/ice/ice_rxtx.h +++ b/drivers/net/ice/ice_rxtx.h @@ -51,6 +51,9 @@ extern int ice_timestamp_dynfield_offset; /* Max header size can be 2K - 64 bytes */ #define ICE_RX_HDR_BUF_SIZE (2048 - 64) +/* Max data buffer size must be 16K - 128 bytes */ +#define ICE_RX_MAX_DATA_BUF_SIZE (16 * 1024 - 128) + #define ICE_HEADER_SPLIT_ENA BIT(0) typedef void (*ice_rx_release_mbufs_t)(struct ice_rx_queue *rxq);