From patchwork Fri Apr 14 03:51:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjun Wu X-Patchwork-Id: 126058 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 748964293A; Fri, 14 Apr 2023 05:52:47 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0EF3642D4E; Fri, 14 Apr 2023 05:52:15 +0200 (CEST) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mails.dpdk.org (Postfix) with ESMTP id D4BB142BFE for ; Fri, 14 Apr 2023 05:52:09 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681444329; x=1712980329; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/nbNihj/ZJw1IIHrV50OJLy+LnnYFzXarPiunf2wxn0=; b=Z1OpKtcJPWIAaO3IwYAzf62r/FuHRt21F81LT9N9EL51wM9JrXKleY/F rfNdAvBfmxjDpK2TTwmGhTKnSGumqNWRyF60dPoj2jwethZfG0GkpLhk/ kt663ajW9B6lKJrNEucArrc4reb1JatJY6tA4Q9Cje3AgNvi+jz6rkk8k 11Xko596VuLca5AFeCg0A48fWZvRiWLzIITFeJPh2ehsfr4jeBiLFEg4r 7SlYI7EzLugwjHt1U3E9dXG0IWwXEaxzAjUEjFRDxmNlRn9E0uIjMQTDh ByWPchRB0YUMnmQA9/5OHG1hvlL9hX1cCi0H7MLzPJHmW296Poll7Xq56 g==; X-IronPort-AV: E=McAfee;i="6600,9927,10679"; a="343135764" X-IronPort-AV: E=Sophos;i="5.99,195,1677571200"; d="scan'208";a="343135764" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 20:52:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10679"; a="683192274" X-IronPort-AV: E=Sophos;i="5.99,195,1677571200"; d="scan'208";a="683192274" Received: from dpdk-wuwenjun-icelake-ii.sh.intel.com ([10.67.110.157]) by orsmga007.jf.intel.com with ESMTP; 13 Apr 2023 20:52:06 -0700 From: Wenjun Wu To: dev@dpdk.org, Yuying.Zhang@intel.com, beilei.xing@intel.com, jingjing.wu@intel.com, qiming.yang@intel.com, qi.z.zhang@intel.com Cc: Wenjun Wu Subject: [PATCH v1 5/5] net/cpfl: fix RX data buffer size Date: Fri, 14 Apr 2023 11:51:51 +0800 Message-Id: <20230414035151.1377726-6-wenjun1.wu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230414035151.1377726-1-wenjun1.wu@intel.com> References: <20230414035151.1377726-1-wenjun1.wu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch does two fixes. 1. No matter what the mbuf size is, the data buffer size should not be greater than 16K - 128. 2. Align data buffer size to 128. Signed-off-by: Wenjun Wu --- drivers/net/cpfl/cpfl_rxtx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c index de59b31b3d..75021c3c54 100644 --- a/drivers/net/cpfl/cpfl_rxtx.c +++ b/drivers/net/cpfl/cpfl_rxtx.c @@ -155,7 +155,8 @@ cpfl_rx_split_bufq_setup(struct rte_eth_dev *dev, struct idpf_rx_queue *rxq, bufq->adapter = base; len = rte_pktmbuf_data_room_size(bufq->mp) - RTE_PKTMBUF_HEADROOM; - bufq->rx_buf_len = len; + bufq->rx_buf_len = RTE_ALIGN_FLOOR(len, (1 << IDPF_RLAN_CTX_DBUF_S)); + bufq->rx_buf_len = RTE_MIN(bufq->rx_buf_len, IDPF_RX_MAX_DATA_BUF_SIZE); /* Allocate a little more to support bulk allocate. */ len = nb_desc + IDPF_RX_MAX_BURST;