From patchwork Fri Apr 14 05:47:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjun Wu X-Patchwork-Id: 126067 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B6DBB4293B; Fri, 14 Apr 2023 07:47:58 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A8D2142D0C; Fri, 14 Apr 2023 07:47:58 +0200 (CEST) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mails.dpdk.org (Postfix) with ESMTP id CBC09400D5; Fri, 14 Apr 2023 07:47:56 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681451276; x=1712987276; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+UArh+vc69k03H6djGJEM8H8bBRGJjnfKacOlSI4A0Y=; b=lIeANgqapXh/5bMCJW0FQySXdtu9M32TG51/nE5gHdf26mVtxWLbwyNV sK5YJ4/73jE9MiBc6GruCOeQBphbh4FRLTiZyPYff4nJj5EsAaAjNthdl npEJFQJQjHNhgy0MJj8SB0oq9PbXpcDBZZs3vJ+xXYn3MdA/RBarWFkyM VF2ZThgBmxOLGevGFq4vG2uPaGgD4cSbOqi6fCPKOP91nbPJqBuX+lEVW tXGafJs7Cp863mgXC4fPNd5u4jNYtQbtCqgg20W1y0fLQ3uM1ZUsx2sh5 LwhZs6H4dQsHEA7mgn4+Loyyn9MIbXzWMLDPZ7/tugm05eh0jh5prixRZ A==; X-IronPort-AV: E=McAfee;i="6600,9927,10679"; a="343150137" X-IronPort-AV: E=Sophos;i="5.99,195,1677571200"; d="scan'208";a="343150137" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 22:47:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10679"; a="779060285" X-IronPort-AV: E=Sophos;i="5.99,195,1677571200"; d="scan'208";a="779060285" Received: from dpdk-wuwenjun-icelake-ii.sh.intel.com ([10.67.110.157]) by FMSMGA003.fm.intel.com with ESMTP; 13 Apr 2023 22:47:53 -0700 From: Wenjun Wu To: dev@dpdk.org, Yuying.Zhang@intel.com, beilei.xing@intel.com, jingjing.wu@intel.com, qiming.yang@intel.com, qi.z.zhang@intel.com Cc: Wenjun Wu , stable@dpdk.org Subject: [PATCH v2 1/5] net/i40e: fix Rx data buffer size Date: Fri, 14 Apr 2023 13:47:40 +0800 Message-Id: <20230414054744.1399735-2-wenjun1.wu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230414054744.1399735-1-wenjun1.wu@intel.com> References: <20230414035151.1377726-1-wenjun1.wu@intel.com> <20230414054744.1399735-1-wenjun1.wu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org No matter what the mbuf size is, the data buffer size should not be greater than 16K - 128. Fixes: 4861cde46116 ("i40e: new poll mode driver") Cc: stable@dpdk.org Signed-off-by: Wenjun Wu --- drivers/net/i40e/i40e_rxtx.c | 2 ++ drivers/net/i40e/i40e_rxtx.h | 3 +++ 2 files changed, 5 insertions(+) diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c index 788ffb51c2..fbbefb5015 100644 --- a/drivers/net/i40e/i40e_rxtx.c +++ b/drivers/net/i40e/i40e_rxtx.c @@ -2904,6 +2904,8 @@ i40e_rx_queue_config(struct i40e_rx_queue *rxq) rxq->rx_hdr_len = 0; rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT)); + rxq->rx_buf_len = RTE_MIN(rxq->rx_buf_len, + I40E_RX_MAX_DATA_BUF_SIZE); rxq->hs_mode = i40e_header_split_none; break; } diff --git a/drivers/net/i40e/i40e_rxtx.h b/drivers/net/i40e/i40e_rxtx.h index 5e6eecc501..0376c219be 100644 --- a/drivers/net/i40e/i40e_rxtx.h +++ b/drivers/net/i40e/i40e_rxtx.h @@ -21,6 +21,9 @@ /* In none-PXE mode QLEN must be whole number of 32 descriptors. */ #define I40E_ALIGN_RING_DESC 32 +/* Max data buffer size must be 16K - 128 bytes */ +#define I40E_RX_MAX_DATA_BUF_SIZE (16 * 1024 - 128) + #define I40E_MIN_RING_DESC 64 #define I40E_MAX_RING_DESC 4096