From patchwork Thu Apr 27 06:19:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126578 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9DD4D42A08; Thu, 27 Apr 2023 08:39:14 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E71FF42DB5; Thu, 27 Apr 2023 08:38:08 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 3797942D82 for ; Thu, 27 Apr 2023 08:38:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682577485; x=1714113485; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7BZgG3Rw+N5cou1cIkOtIcZ2yHzCJIfYKPviovbR4ak=; b=iadWhKGZ1QEp8QiFMvaHgSPuhjmDH1/p4Yqb7k/+RyIrPqRcnBOKNMy3 LhVT3B1CdKkVXd7RpT4zfn34O1NMZH9I/zU//BCSzFsmVuqdSklcOM3Mx 6u54S+JRE5WYRUSc4PmWmJyLspQQloKPM/QZ0yI/i26iNkCK787YKhZtx RSDbuH0wy3DiXWKYhuDu//0T30g6TaZEa+oySw1yLbT4uxEGAW4qRqjlY PDoTu3pyYWvUQ+pSzGDCjHL4gm4bk9Uk3rkFSDZ0mYT4YWkCoknVJElz5 9DQghlK2aqPMb9N7kgUn6drFmrWbK84uI+kNqJQXg9pirOVOyeE8ShT7T A==; X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="375324311" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324311" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:38:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845727" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845727" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:02 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Jesse Brandeburg Subject: [PATCH 11/30] net/ice/base: add new fls function Date: Thu, 27 Apr 2023 06:19:42 +0000 Message-Id: <20230427062001.478032-12-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add a new function called ice_fls() and merged some code clean. Signed-off-by: Jesse Brandeburg Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_common.c | 40 ++++++++++++++++++++++-- drivers/net/ice/base/ice_common.h | 1 + drivers/net/ice/base/ice_protocol_type.h | 11 +++---- drivers/net/ice/base/ice_switch.c | 25 ++++++++------- drivers/net/ice/base/ice_type.h | 18 +++++++++++ 5 files changed, 75 insertions(+), 20 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index cebf1504f1..6967ff1a8f 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -3238,8 +3238,8 @@ bool ice_is_100m_speed_supported(struct ice_hw *hw) * Note: In the structure of [phy_type_low, phy_type_high], there should * be one bit set, as this function will convert one PHY type to its * speed. - * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned - * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned + * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned + * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned */ static u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) @@ -6134,6 +6134,42 @@ bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) ICE_FW_API_REPORT_DFLT_CFG_PATCH); } +/* each of the indexes into the following array match the speed of a return + * value from the list of AQ returned speeds like the range: + * ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding + * ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) The array is defined as 15 + * elements long because the link_speed returned by the firmware is a 16 bit + * value, but is indexed by [fls(speed) - 1] + */ +static const u32 ice_aq_to_link_speed[] = { + ICE_LINK_SPEED_10MBPS, /* BIT(0) */ + ICE_LINK_SPEED_100MBPS, + ICE_LINK_SPEED_1000MBPS, + ICE_LINK_SPEED_2500MBPS, + ICE_LINK_SPEED_5000MBPS, + ICE_LINK_SPEED_10000MBPS, + ICE_LINK_SPEED_20000MBPS, + ICE_LINK_SPEED_25000MBPS, + ICE_LINK_SPEED_40000MBPS, + ICE_LINK_SPEED_50000MBPS, + ICE_LINK_SPEED_100000MBPS, /* BIT(10) */ + ICE_LINK_SPEED_200000MBPS, +}; + +/** + * ice_get_link_speed - get integer speed from table + * @index: array index from fls(aq speed) - 1 + * + * Returns: u32 value containing integer speed + */ +u32 ice_get_link_speed(u16 index) +{ + if (index >= ARRAY_SIZE(ice_aq_to_link_speed)) + return ICE_LINK_SPEED_UNKNOWN; + + return ice_aq_to_link_speed[index]; +} + /** * ice_fw_supports_fec_dis_auto * @hw: pointer to the hardware structure diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h index 83ef438041..d8fb7a6163 100644 --- a/drivers/net/ice/base/ice_common.h +++ b/drivers/net/ice/base/ice_common.h @@ -217,6 +217,7 @@ enum ice_status ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, bool write, struct ice_sq_cd *cd); +u32 ice_get_link_speed(u16 index); enum ice_status ice_aq_prog_topo_dev_nvm(struct ice_hw *hw, diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h index eeaf044059..1d9baea624 100644 --- a/drivers/net/ice/base/ice_protocol_type.h +++ b/drivers/net/ice/base/ice_protocol_type.h @@ -97,6 +97,10 @@ enum ice_sw_tunnel_type { ICE_SW_TUN_IPV6_GTPU_EH_IPV6_UDP, ICE_SW_TUN_IPV6_GTPU_IPV6_TCP, ICE_SW_TUN_IPV6_GTPU_EH_IPV6_TCP, + ICE_SW_TUN_IPV4_GTPU_IPV4, + ICE_SW_TUN_IPV4_GTPU_IPV6, + ICE_SW_TUN_IPV6_GTPU_IPV4, + ICE_SW_TUN_IPV6_GTPU_IPV6, ICE_SW_TUN_PPPOE, ICE_SW_TUN_PPPOE_PAY, ICE_SW_TUN_PPPOE_IPV4, @@ -127,12 +131,6 @@ enum ice_sw_tunnel_type { ICE_SW_TUN_PPPOE_PAY_QINQ, ICE_SW_TUN_PPPOE_IPV4_QINQ, ICE_SW_TUN_PPPOE_IPV6_QINQ, - ICE_SW_TUN_IPV4_GTPU_IPV4, - ICE_SW_TUN_IPV4_GTPU_IPV6, - ICE_SW_TUN_IPV6_GTPU_IPV4, - ICE_SW_TUN_IPV6_GTPU_IPV6, - ICE_SW_TUN_GTP_IPV4, - ICE_SW_TUN_GTP_IPV6, ICE_ALL_TUNNELS /* All tunnel types including NVGRE */ }; @@ -224,6 +222,7 @@ enum ice_prot_id { #define ICE_TUN_FLAG_MDID_OFF(word) (ICE_MDID_SIZE * (ICE_TUN_FLAG_MDID + (word))) #define ICE_TUN_FLAG_MASK 0xFF #define ICE_DIR_FLAG_MASK 0x10 +#define ICE_TUN_FLAG_IN_VLAN_MASK 0x80 /* VLAN inside tunneled header */ #define ICE_TUN_FLAG_VLAN_MASK 0x01 #define ICE_TUN_FLAG_FV_IND 2 diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index b3d9847669..1b8311fdc7 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -915,15 +915,6 @@ static const u8 dummy_ipv6_gtpu_ipv6_udp_packet[] = { 0x00, 0x00, /* 2 bytes for 4 byte alignment */ }; -static const struct ice_dummy_pkt_offsets dummy_ipv4_gtpu_ipv4_packet_offsets[] = { - { ICE_MAC_OFOS, 0 }, - { ICE_IPV4_OFOS, 14 }, - { ICE_UDP_OF, 34 }, - { ICE_GTP, 42 }, - { ICE_IPV4_IL, 62 }, - { ICE_PROTOCOL_LAST, 0 }, -}; - static const u8 dummy_ipv4_gtpu_ipv4_packet[] = { 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ 0x00, 0x00, 0x00, 0x00, @@ -954,8 +945,17 @@ static const u8 dummy_ipv4_gtpu_ipv4_packet[] = { 0x00, 0x00, }; -static const -struct ice_dummy_pkt_offsets dummy_ipv4_gtpu_ipv6_packet_offsets[] = { +static const struct +ice_dummy_pkt_offsets dummy_ipv4_gtpu_ipv4_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_IPV4_OFOS, 14 }, + { ICE_UDP_OF, 34 }, + { ICE_GTP, 42 }, + { ICE_IPV4_IL, 62 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const struct ice_dummy_pkt_offsets dummy_ipv4_gtpu_ipv6_packet_offsets[] = { { ICE_MAC_OFOS, 0 }, { ICE_IPV4_OFOS, 14 }, { ICE_UDP_OF, 34 }, @@ -7532,7 +7532,8 @@ static bool ice_tun_type_match_word(enum ice_sw_tunnel_type tun_type, u16 *off, case ICE_SW_TUN_GENEVE_VLAN: case ICE_SW_TUN_VXLAN_VLAN: - *mask = ICE_TUN_FLAG_MASK & ~ICE_TUN_FLAG_VLAN_MASK; + *mask = ICE_TUN_FLAG_MASK & ~(ICE_TUN_FLAG_VLAN_MASK | + ICE_TUN_FLAG_IN_VLAN_MASK); *off = ICE_TUN_FLAG_MDID_OFF(1); return true; diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index ec4892179a..5779590a7e 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -43,6 +43,24 @@ static inline int ice_ilog2(u64 n) return -1; } +/** + * ice_fls - find the most significant bit set in a u64 + * @n: u64 value to scan for a bit + * + * Returns: 0 if no bits found, otherwise the index of the highest bit that was + * set, like ice_fls(0x20) == 6. This means this is returning a *1 based* + * count, and that the maximum largest value returned is 64! + */ +static inline unsigned int ice_fls(u64 n) +{ + int ret; + + ret = ice_ilog2(n); + + /* add one to turn to the ilog2 value into a 1 based index */ + return ret >= 0 ? ret + 1 : 0; +} + static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc) { return ice_is_bit_set(&bitmap, tc);