From patchwork Thu Apr 27 06:19:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126582 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 13A7E42A08; Thu, 27 Apr 2023 08:39:41 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6E99F42DC8; Thu, 27 Apr 2023 08:38:16 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id D513742DC2 for ; Thu, 27 Apr 2023 08:38:12 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682577493; x=1714113493; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/BPk+Lf+JfMhOjxzFjkeMwfvVGWOSWScj8KPyUtYkiU=; b=MJnWc08BE1SYoh3K9TyHLJaQikqJVlCt370NWhGKxwwTjtdimGS54Zj8 F0VzaVYEDQ0yW6NDEDCedn0D5MhU5c7T2wUNjb81y/EiDGCQeiYBjXIfh P2BM3i6xuGf3zH+7sEnSqniKeJGhRvEmy0R/G5P9XKIWSIEBvvhpTQWZW Ivsiallp8aQ0peQU/cOqgMBCfoi2lHp5ROutVXpJQrUQQvN7n8/kOXOc/ tiBoqTGwW3EVJW4WwHQX0wRbakHvdENQM0iNARcBRTTd2jD818oSAAjKY 2gFrR52J0BCbZfnh/i+TpWAscVc5eCcdxOHiOhzI05G7uxjSMgEE3IZI/ w==; X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="375324340" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324340" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:38:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845808" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845808" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:10 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Sergey Temerkhanov Subject: [PATCH 15/30] net/ice/base: allow skip main timer Date: Thu, 27 Apr 2023 06:19:46 +0000 Message-Id: <20230427062001.478032-16-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Allow initialization functions to skip main timer programming. Signed-off-by: Sergey Temerkhanov Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_ptp_hw.c | 32 ++++++++++++++++++++----------- drivers/net/ice/base/ice_ptp_hw.h | 9 ++++++--- drivers/net/ice/ice_ethdev.c | 2 +- 3 files changed, 28 insertions(+), 15 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 61145262ac..43b7e313f4 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -3550,6 +3550,7 @@ ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, bool lock_sbq) * ice_ptp_init_time - Initialize device time to provided value * @hw: pointer to HW struct * @time: 64bits of time (GLTSYN_TIME_L and GLTSYN_TIME_H) + * @wr_main_tmr: program the main timer * * Initialize the device to the specified time provided. This requires a three * step process: @@ -3559,7 +3560,8 @@ ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, bool lock_sbq) * 3) issue an init_time timer command to synchronously switch both the source * and port timers to the new init time value at the next clock cycle. */ -enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time) +enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time, + bool wr_main_tmr) { enum ice_status status; u8 tmr_idx; @@ -3567,9 +3569,11 @@ enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time) tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; /* Source timers */ - wr32(hw, GLTSYN_SHTIME_L(tmr_idx), ICE_LO_DWORD(time)); - wr32(hw, GLTSYN_SHTIME_H(tmr_idx), ICE_HI_DWORD(time)); - wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0); + if (wr_main_tmr) { + wr32(hw, GLTSYN_SHTIME_L(tmr_idx), ICE_LO_DWORD(time)); + wr32(hw, GLTSYN_SHTIME_H(tmr_idx), ICE_HI_DWORD(time)); + wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0); + } /* PHY Clks */ /* Fill Rx and Tx ports and send msg to PHY */ @@ -3594,8 +3598,9 @@ enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time) * ice_ptp_write_incval - Program PHC with new increment value * @hw: pointer to HW struct * @incval: Source timer increment value per clock cycle + * @wr_main_tmr: Program the main timer * - * Program the PHC with a new increment value. This requires a three-step + * Program the timers with a new increment value. This requires a three-step * process: * * 1) Write the increment value to the source timer shadow registers @@ -3604,16 +3609,19 @@ enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time) * the source and port timers to the new increment value at the next clock * cycle. */ -enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval) +enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval, + bool wr_main_tmr) { enum ice_status status; u8 tmr_idx; tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; - /* Shadow Adjust */ - wr32(hw, GLTSYN_SHADJ_L(tmr_idx), ICE_LO_DWORD(incval)); - wr32(hw, GLTSYN_SHADJ_H(tmr_idx), ICE_HI_DWORD(incval)); + if (wr_main_tmr) { + /* Shadow Adjust */ + wr32(hw, GLTSYN_SHADJ_L(tmr_idx), ICE_LO_DWORD(incval)); + wr32(hw, GLTSYN_SHADJ_H(tmr_idx), ICE_HI_DWORD(incval)); + } switch (hw->phy_cfg) { case ICE_PHY_E810: @@ -3636,17 +3644,19 @@ enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval) * ice_ptp_write_incval_locked - Program new incval while holding semaphore * @hw: pointer to HW struct * @incval: Source timer increment value per clock cycle + * @wr_main_tmr: Program the main timer * * Program a new PHC incval while holding the PTP semaphore. */ -enum ice_status ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval) +enum ice_status ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval, + bool wr_main_tmr) { enum ice_status status; if (!ice_ptp_lock(hw)) return ICE_ERR_NOT_READY; - status = ice_ptp_write_incval(hw, incval); + status = ice_ptp_write_incval(hw, incval, wr_main_tmr); ice_ptp_unlock(hw); diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index d2581e63f9..48a30f1f4e 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -131,9 +131,12 @@ u64 ice_ptp_read_src_incval(struct ice_hw *hw); bool ice_ptp_lock(struct ice_hw *hw); void ice_ptp_unlock(struct ice_hw *hw); void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd); -enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time); -enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval); -enum ice_status ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval); +enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time, + bool wr_main_tmr); +enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval, + bool wr_main_tmr); +enum ice_status ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval, + bool wr_main_tmr); enum ice_status ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq); enum ice_status ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj); diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 9a88cf9796..6700893bc5 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -5832,7 +5832,7 @@ ice_timesync_enable(struct rte_eth_dev *dev) return -1; } - ret = ice_ptp_write_incval(hw, ICE_PTP_NOMINAL_INCVAL_E810); + ret = ice_ptp_write_incval(hw, ICE_PTP_NOMINAL_INCVAL_E810, 1); if (ret) { PMD_DRV_LOG(ERR, "Failed to write PHC increment time value");