From patchwork Thu Apr 27 06:19:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126588 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3232942A08; Thu, 27 Apr 2023 08:40:18 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F045F42FD6; Thu, 27 Apr 2023 08:38:25 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 2F3FD42FAE for ; Thu, 27 Apr 2023 08:38:23 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682577503; x=1714113503; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kHaX2/evjDYYkSJkKJa31toq/2wd0W7TtHB3kfDV+UA=; b=flT23UbYqMEzQABajt4p6ix/uNpurcSco9pl0aH4PfABRQUDDhBiwIwc A18iWZE2WYKFVLSyZtwaaLnwiiIyVyED5hK8h4D/ipDmyqOvwt+2zPStZ Lk/yyXh6OK98kIy2LpqmKZ1emthi4w8BfqOQKua3tU9t4/njYccBdBsuH eNjt4rrht/VC3uVN11SktfOfthk2XvRrCsv77l5VemIoVED8cLPARvPpS gpFgYL0ZwJ5EBpoFvxzscRZdBBNb4ZF5RpUIu6IyYNIbda3WEr/YQ7Hn/ rqmKyhMbCB1rZyaW5jGfhwSSOJX7HZRLbpQEB0Cn5Lc5FAqDHTjyCaGWF g==; X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="375324374" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324374" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:38:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845855" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845855" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:20 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Karol Kolacinski Subject: [PATCH 21/30] net/ice/base: add PHY OFFSET READY register clear Date: Thu, 27 Apr 2023 06:19:52 +0000 Message-Id: <20230427062001.478032-22-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add a possibility to mark all transmitted/received timestamps as invalid by clearing PHY OFFSET_READY registers. Signed-off-by: Karol Kolacinski Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_adminq_cmd.h | 4 + drivers/net/ice/base/ice_ptp_hw.c | 126 ++++++++------------------ drivers/net/ice/base/ice_ptp_hw.h | 1 + 3 files changed, 43 insertions(+), 88 deletions(-) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index cd4a6ffddf..c51054ecc1 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -2897,6 +2897,10 @@ enum ice_aqc_driver_params { ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0 = 0, /* OS clock index for PTP timer Domain 1 */ ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1, + /* Request ID to recalibrate PHC logic */ + ICE_AQC_DRIVER_PARAM_PHC_RECALC, + /* Indicates that PTP clock controller failed */ + ICE_AQC_DRIVER_PARAM_PTP_CC_FAILED, /* Add new parameters above */ ICE_AQC_DRIVER_PARAM_MAX = 16, diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index a638bb114c..f27131efcc 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -2027,47 +2027,6 @@ enum ice_status ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port) return ICE_SUCCESS; } -/** - * ice_phy_cfg_fixed_tx_offset_e822 - Configure Tx offset for bypass mode - * @hw: pointer to the HW struct - * @port: the PHY port to configure - * - * Calculate and program the fixed Tx offset, and indicate that the offset is - * ready. This can be used when operating in bypass mode. - */ -static enum ice_status -ice_phy_cfg_fixed_tx_offset_e822(struct ice_hw *hw, u8 port) -{ - enum ice_ptp_link_spd link_spd; - enum ice_ptp_fec_mode fec_mode; - enum ice_status status; - u64 total_offset; - - status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode); - if (status) - return status; - - total_offset = ice_calc_fixed_tx_offset_e822(hw, link_spd); - - /* Program the fixed Tx offset into the P_REG_TOTAL_TX_OFFSET_L - * register, then indicate that the Tx offset is ready. After this, - * timestamps will be enabled. - * - * Note that this skips including the more precise offsets generated - * by the Vernier calibration. - */ - status = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_TX_OFFSET_L, - total_offset); - if (status) - return status; - - status = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 1); - if (status) - return status; - - return ICE_SUCCESS; -} - /** * ice_phy_calc_pmd_adj_e822 - Calculate PMD adjustment for Rx * @hw: pointer to the HW struct @@ -2348,43 +2307,33 @@ enum ice_status ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port) return ICE_SUCCESS; } + /** - * ice_phy_cfg_fixed_rx_offset_e822 - Configure fixed Rx offset for bypass mode + * ice_ptp_clear_phy_offset_ready_e822 - Clear PHY TX_/RX_OFFSET_READY registers * @hw: pointer to the HW struct - * @port: the PHY port to configure * - * Calculate and program the fixed Rx offset, and indicate that the offset is - * ready. This can be used when operating in bypass mode. + * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted + * and received timestamps as invalid. */ -static enum ice_status -ice_phy_cfg_fixed_rx_offset_e822(struct ice_hw *hw, u8 port) +static enum ice_status ice_ptp_clear_phy_offset_ready_e822(struct ice_hw *hw) { - enum ice_ptp_link_spd link_spd; - enum ice_ptp_fec_mode fec_mode; - enum ice_status status; - u64 total_offset; - - status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode); - if (status) - return status; + u8 port; - total_offset = ice_calc_fixed_rx_offset_e822(hw, link_spd); + for (port = 0; port < hw->phy_ports; port++) { + enum ice_status status; - /* Program the fixed Rx offset into the P_REG_TOTAL_RX_OFFSET_L - * register, then indicate that the Rx offset is ready. After this, - * timestamps will be enabled. - * - * Note that this skips including the more precise offsets generated - * by Vernier calibration. - */ - status = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_RX_OFFSET_L, - total_offset); - if (status) - return status; + status = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 0); + if (status) { + ice_warn(hw, "Failed to clear PHY TX_OFFSET_READY register\n"); + return status; + } - status = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 1); - if (status) - return status; + status = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 0); + if (status) { + ice_warn(hw, "Failed to clear PHY RX_OFFSET_READY register\n"); + return status; + } + } return ICE_SUCCESS; } @@ -2666,24 +2615,6 @@ ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass) if (status) return status; - if (bypass) { - val |= P_REG_PS_BYPASS_MODE_M; - /* Enter BYPASS mode, enabling timestamps immediately. */ - status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); - if (status) - return status; - - /* Program the fixed Tx offset */ - status = ice_phy_cfg_fixed_tx_offset_e822(hw, port); - if (status) - return status; - - /* Program the fixed Rx offset */ - status = ice_phy_cfg_fixed_rx_offset_e822(hw, port); - if (status) - return status; - } - ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port); return ICE_SUCCESS; @@ -3841,6 +3772,25 @@ ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj) return ice_ptp_tmr_cmd(hw, ICE_PTP_ADJ_TIME_AT_TIME, true); } +/** + * ice_ptp_clear_phy_offset_ready - Clear PHY TX_/RX_OFFSET_READY registers + * @hw: pointer to the HW struct + * + * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted + * and received timestamps as invalid. + */ +enum ice_status ice_ptp_clear_phy_offset_ready(struct ice_hw *hw) +{ + switch (hw->phy_model) { + case ICE_PHY_E810: + return ICE_SUCCESS; + case ICE_PHY_E822: + return ice_ptp_clear_phy_offset_ready_e822(hw); + default: + return ICE_ERR_NOT_SUPPORTED; + } +} + /** * ice_read_phy_tstamp - Read a PHY timestamp from the timestamp block * @hw: pointer to the HW struct diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index e25018a68f..f4d64ea02b 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -151,6 +151,7 @@ enum ice_status ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval, enum ice_status ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq); enum ice_status ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj); +enum ice_status ice_ptp_clear_phy_offset_ready(struct ice_hw *hw); enum ice_status ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp); enum ice_status