From patchwork Thu Apr 27 06:19:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126589 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D005542A08; Thu, 27 Apr 2023 08:40:23 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1478842FEA; Thu, 27 Apr 2023 08:38:27 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id B96E442FC8 for ; Thu, 27 Apr 2023 08:38:24 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682577504; x=1714113504; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WPdX2SsrZtrAbwvgLYQvSEDZ9HaULQrivVSfqQ8+2JU=; b=jYubxelFjPoXA0uOiR/6z3aueD0zzehd3Hs8qd76Pe5SoW+3R8UKNYf+ Jaf95oiIENsXQVT4GvivylX3ZaFqFfECZfvNCsizXaNS+XhIZ6XIlIVGk NE1ef3yaDoM9K9CcEft355vif7HSfHPLTDVG5965ZwC4lbpCYkJAUKF8+ C1htZUf8zzqBOsHMSkqRS1GAE5uX6mD7GOOFEwS+jlG7bVn06+F00mSkp AzFHsPrQa4JatnoClrGYcD5BhIEBm+yqVd+DReIT0pyVxt4WRs52YCTtH g1HrBChNIxjLNgB6lQSah3VXpG7ySSVQqzrl4eiXLLQFvqVoZUkAySFeZ A==; X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="375324381" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324381" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:38:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845863" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845863" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:22 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Karol Kolacinski Subject: [PATCH 22/30] net/ice/base: return CGU PLL config function params Date: Thu, 27 Apr 2023 06:19:53 +0000 Message-Id: <20230427062001.478032-23-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Change params in ice_cfg_cgu_pll_e822 to pointers to return real values of frequency and clock source. Remove static from frequency and clock source conversion functions. Signed-off-by: Karol Kolacinski Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_ptp_hw.c | 39 ++++++++++++++++++------------- drivers/net/ice/base/ice_ptp_hw.h | 4 ++-- 2 files changed, 25 insertions(+), 18 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index f27131efcc..cc6c1f3152 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -218,8 +218,8 @@ static const char *ice_clk_src_str(u8 clk_src) * time reference, enabling the PLL which drives the PTP hardware clock. */ enum ice_status -ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq, - enum ice_clk_src clk_src) +ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq, + enum ice_clk_src *clk_src) { union tspll_ro_bwm_lf bwm_lf; union nac_cgu_dword19 dw19; @@ -228,18 +228,18 @@ ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq, union nac_cgu_dword9 dw9; enum ice_status status; - if (clk_freq >= NUM_ICE_TIME_REF_FREQ) { - ice_warn(hw, "Invalid TIME_REF frequency %u\n", clk_freq); + if (*clk_freq >= NUM_ICE_TIME_REF_FREQ) { + ice_warn(hw, "Invalid TIME_REF frequency %u\n", *clk_freq); return ICE_ERR_PARAM; } - if (clk_src >= NUM_ICE_CLK_SRC) { - ice_warn(hw, "Invalid clock source %u\n", clk_src); + if (*clk_src >= NUM_ICE_CLK_SRC) { + ice_warn(hw, "Invalid clock source %u\n", *clk_src); return ICE_ERR_PARAM; } - if (clk_src == ICE_CLK_SRC_TCX0 && - clk_freq != ICE_TIME_REF_FREQ_25_000) { + if (*clk_src == ICE_CLK_SRC_TCX0 && + *clk_freq != ICE_TIME_REF_FREQ_25_000) { ice_warn(hw, "TCX0 only supports 25 MHz frequency\n"); return ICE_ERR_PARAM; } @@ -273,7 +273,7 @@ ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq, } /* Set the frequency */ - dw9.field.time_ref_freq_sel = clk_freq; + dw9.field.time_ref_freq_sel = *clk_freq; status = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD9, dw9.val); if (status) return status; @@ -283,7 +283,7 @@ ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq, if (status) return status; - dw19.field.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div; + dw19.field.tspll_fbdiv_intgr = e822_cgu_params[*clk_freq].feedback_div; dw19.field.tspll_ndivratio = 1; status = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD19, dw19.val); @@ -295,7 +295,7 @@ ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq, if (status) return status; - dw22.field.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div; + dw22.field.time1588clk_div = e822_cgu_params[*clk_freq].post_pll_div; dw22.field.time1588clk_sel_div2 = 0; status = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD22, dw22.val); @@ -307,9 +307,9 @@ ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq, if (status) return status; - dw24.field.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div; - dw24.field.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div; - dw24.field.time_ref_sel = clk_src; + dw24.field.ref1588_ck_div = e822_cgu_params[*clk_freq].refclk_pre_div; + dw24.field.tspll_fbdiv_frac = e822_cgu_params[*clk_freq].frac_n_div; + dw24.field.time_ref_sel = *clk_src; status = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val); if (status) @@ -341,6 +341,9 @@ ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq, ice_clk_freq_str(dw9.field.time_ref_freq_sel), bwm_lf.field.plllock_true_lock_cri ? "locked" : "unlocked"); + *clk_freq = (enum ice_time_ref_freq)dw9.field.time_ref_freq_sel; + *clk_src = (enum ice_clk_src)dw24.field.time_ref_sel; + return ICE_SUCCESS; } @@ -354,6 +357,8 @@ static enum ice_status ice_init_cgu_e822(struct ice_hw *hw) { struct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info; union tspll_cntr_bist_settings cntr_bist; + enum ice_time_ref_freq time_ref_freq; + enum ice_clk_src clk_src; enum ice_status status; status = ice_read_cgu_reg_e822(hw, TSPLL_CNTR_BIST_SETTINGS, @@ -373,8 +378,9 @@ static enum ice_status ice_init_cgu_e822(struct ice_hw *hw) /* Configure the CGU PLL using the parameters from the function * capabilities. */ - status = ice_cfg_cgu_pll_e822(hw, ts_info->time_ref, - (enum ice_clk_src)ts_info->clk_src); + time_ref_freq = (enum ice_time_ref_freq)ts_info->time_ref; + clk_src = (enum ice_clk_src)ts_info->clk_src; + status = ice_cfg_cgu_pll_e822(hw, &time_ref_freq, &clk_src); if (status) return status; @@ -2024,6 +2030,7 @@ enum ice_status ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port) if (status) return status; + return ICE_SUCCESS; } diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index f4d64ea02b..4d5d728e26 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -184,8 +184,8 @@ ice_ptp_one_port_cmd_e822(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd, bool lock_sbq); void ice_ptp_reset_ts_memory_quad_e822(struct ice_hw *hw, u8 quad); enum ice_status -ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq, - enum ice_clk_src clk_src); +ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq, + enum ice_clk_src *clk_src); /** * ice_e822_time_ref - Get the current TIME_REF from capabilities