From patchwork Thu Apr 27 06:19:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126591 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 96A2242A08; Thu, 27 Apr 2023 08:40:35 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BA73242FC8; Thu, 27 Apr 2023 08:38:30 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 74D5E42FEE for ; Thu, 27 Apr 2023 08:38:28 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682577508; x=1714113508; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RTWZG6CbobzfAdjJq9ogTnAwsK38yYIWdCErbBqrIYI=; b=UuRGhZ4CKVBjOf38mVpWseTfaLKeab1zxSqqfqVJO8jRchAKfuFXKSEf cPRnliVsAwAz0nylR1SAPGIjVIX6ZD6dySCw4ug6dmLwoihUTsZyzTNEJ dFLxd8lvYOTXwiJ5UYEepWAYvjrvojv+lxbQjE9GRlfZhs8uobGbTxkvl 8pd/eYJiIoGNXZqYE06k52H4GDGIcKdHbiTJtujPvNV2p1gb76Ri1Ngs+ ZqFLTH8GgeVHRtTO6P4yMmjA4CDo1YeuGnIfhRuk3zts2rVK/ZPqOvD60 wEt8dho8iiVJB48R6ePTqEIVKiDBHtS4ktrUDCHSIutOz6Vk82wdq14E0 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="375324391" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324391" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:38:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845872" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845872" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:25 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Karol Kolacinski , Jacob Keller Subject: [PATCH 24/30] net/ice/base: cleanup timestamp registers correct Date: Thu, 27 Apr 2023 06:19:55 +0000 Message-Id: <20230427062001.478032-25-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org E822 PHY TS registers should not be written and the only way to cleanup them is to reset QUAD memory. To ensure that the status bit for the timestamp index is cleared, ensure that ice_clear_phy_tstamp implementations first read the timestamp out. Implementations which can write the register continue to do so. Add a note to indicate this function should only be called on timestamps which have their valid bit set. Signed-off-by: Karol Kolacinski Signed-off-by: Jacob Keller Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_ptp_hw.c | 54 ++++++++++++++++++------------- 1 file changed, 31 insertions(+), 23 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 29840b2b91..e559d4907f 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -1020,34 +1020,31 @@ ice_read_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp) } /** - * ice_clear_phy_tstamp_e822 - Clear a timestamp from the quad block + * ice_clear_phy_tstamp_e822 - Drop a timestamp from the quad block * @hw: pointer to the HW struct * @quad: the quad to read from * @idx: the timestamp index to reset * - * Clear a timestamp, resetting its valid bit, from the PHY quad block that is - * shared between the internal PHYs on the E822 devices. + * Read the timetamp out of the quad to clear its timestamp status bit from + * the PHY quad block that is shared between the internal PHYs of the E822 + * devices. + * + * Note that software cannot directly write the quad memory bank registers, + * and must use ice_ptp_reset_ts_memory_quad_e822 for that purpose. + * + * This function should only be called on an idx whose bit is set according to + * ice_get_phy_tx_tstamp_ready. */ static enum ice_status ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx) { enum ice_status status; - u16 lo_addr, hi_addr; - - lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx); - hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx); - - status = ice_write_quad_reg_e822(hw, quad, lo_addr, 0); - if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, status %d\n", - status); - return status; - } + u64 unused_tstamp; - status = ice_write_quad_reg_e822(hw, quad, hi_addr, 0); + status = ice_read_phy_tstamp_e822(hw, quad, idx, &unused_tstamp); if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register, status %d\n", - status); + ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for quad %u, idx %u, status %d\n", + quad, idx, status); return status; } @@ -2926,29 +2923,40 @@ ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) * @lport: the lport to read from * @idx: the timestamp index to reset * - * Clear a timestamp, resetting its valid bit, from the timestamp block of the - * external PHY on the E810 device. + * Read the timestamp and then forcibly overwrite its value to clear the valid + * bit from the timestamp block of the external PHY on the E810 device. + * + * This function should only be called on an idx whose bit is set according to + * ice_get_phy_tx_tstamp_ready. */ static enum ice_status ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx) { enum ice_status status; u32 lo_addr, hi_addr; + u64 unused_tstamp; + + status = ice_read_phy_tstamp_e810(hw, lport, idx, &unused_tstamp); + if (status) { + ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for lport %u, idx %u, status %d\n", + lport, idx, status); + return status; + } lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); status = ice_write_phy_reg_e810(hw, lo_addr, 0); if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, status %d\n", - status); + ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for lport %u, idx %u, status %d\n", + lport, idx, status); return status; } status = ice_write_phy_reg_e810(hw, hi_addr, 0); if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register, status %d\n", - status); + ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register for lport %u, idx %u, status %d\n", + lport, idx, status); return status; }