From patchwork Thu Apr 27 06:19:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126593 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 688FB42A08; Thu, 27 Apr 2023 08:40:45 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 02B1542D8E; Thu, 27 Apr 2023 08:38:35 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id D407942FCA for ; Thu, 27 Apr 2023 08:38:31 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682577512; x=1714113512; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dF97cSmz6+9STeAizzXertFrp/4FZ8ZNquUReSv4bb8=; b=Kvjl1yL9CJnmEbgIY+WId3WD4MJcfadAGVwqRI6vpBTx+nt3a9i37pRV cx2oO0FlPmwjTf9dV3Ow3iRcSdAp1cdzhl94Q2PrJ2k6o48akctkTfsso fwSUs4jtOp52fR8EqRwp1laPYAIA0ZBFQzO/UyO7wx6Z8kDOstD19D5br Xn+WEn5I5HoX5ID5itQ1BDUk8LmXnk1BqVwhfq+gHaou5hg1h2mHIl+ws fec5SfP/r9ZWJgox1aMW00Mu+PMh6io7IbWLT1Ir9JN8Ww+u2IeF3jB5S 2zi1ei6Ds+xx+dcnNzjBFcoBNjLqeLKrR0GqLrmAsrmY/TQ1kVWxo405/ w==; X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="375324403" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324403" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:38:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845880" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845880" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:29 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Milena Olech Subject: [PATCH 26/30] net/ice/base: remove bypass mode Date: Thu, 27 Apr 2023 06:19:57 +0000 Message-Id: <20230427062001.478032-27-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Previous implementation switches between bypass and Vernier mode dynamically. However bypass mode should be removed due to low precision. Signed-off-by: Milena Olech Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_ptp_hw.c | 46 ++++++++++++++++++++++++++----- drivers/net/ice/base/ice_ptp_hw.h | 5 ++-- drivers/net/ice/ice_ethdev.c | 2 +- 3 files changed, 43 insertions(+), 10 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index e559d4907f..f67e0b0c34 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -2584,20 +2584,15 @@ ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset) * ice_start_phy_timer_e822 - Start the PHY clock timer * @hw: pointer to the HW struct * @port: the PHY port to start - * @bypass: if true, start the PHY in bypass mode * * Start the clock of a PHY port. This must be done as part of the flow to * re-calibrate Tx and Rx timestamping offsets whenever the clock time is * initialized or when link speed changes. * - * Bypass mode enables timestamps immediately without waiting for Vernier - * calibration to complete. Hardware will still continue taking Vernier - * measurements on Tx or Rx of packets, but they will not be applied to - * timestamps. Use ice_phy_exit_bypass_e822 to exit bypass mode once hardware - * has completed offset calculation. + * Hardware will take Vernier measurements on Tx or Rx of packets. */ enum ice_status -ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass) +ice_start_phy_timer_e822(struct ice_hw *hw, u8 port) { enum ice_status status; u32 lo, hi, val; @@ -2721,6 +2716,43 @@ ice_get_phy_tx_tstamp_ready_e822(struct ice_hw *hw, u8 quad, u64 *tstamp_ready) return ICE_SUCCESS; } +/** + * ice_phy_cfg_intr_e822 - Configure TX timestamp interrupt + * @hw: pointer to the HW struct + * @quad: the timestamp quad + * @ena: enable or disable interrupt + * @threshold: interrupt threshold + * + * Configure TX timestamp interrupt for the specified quad + */ + +enum ice_status +ice_phy_cfg_intr_e822(struct ice_hw *hw, u8 quad, bool ena, u8 threshold) +{ + enum ice_status err; + u32 val; + + err = ice_read_quad_reg_e822(hw, quad, + Q_REG_TX_MEM_GBL_CFG, + &val); + if (err) + return err; + + if (ena) { + val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M; + val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M; + val |= ((threshold << Q_REG_TX_MEM_GBL_CFG_INTR_THR_S) & + Q_REG_TX_MEM_GBL_CFG_INTR_THR_M); + } else { + val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M; + } + + err = ice_write_quad_reg_e822(hw, quad, + Q_REG_TX_MEM_GBL_CFG, + val); + + return err; +} /* E810 functions * diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index 4d5d728e26..0a7c6d052c 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -237,10 +237,11 @@ void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port); enum ice_status ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset); enum ice_status -ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass); +ice_start_phy_timer_e822(struct ice_hw *hw, u8 port); enum ice_status ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port); enum ice_status ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port); -enum ice_status ice_phy_exit_bypass_e822(struct ice_hw *hw, u8 port); +enum ice_status +ice_phy_cfg_intr_e822(struct ice_hw *hw, u8 quad, bool ena, u8 threshold); /* E810 family functions */ bool ice_is_gps_present_e810t(struct ice_hw *hw); diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 2a4073c4d1..8b41753b83 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -2418,7 +2418,7 @@ ice_dev_init(struct rte_eth_dev *dev) hw->phy_model = ICE_PHY_E822; if (hw->phy_model == ICE_PHY_E822) { - ret = ice_start_phy_timer_e822(hw, hw->pf_id, true); + ret = ice_start_phy_timer_e822(hw, hw->pf_id); if (ret) PMD_INIT_LOG(ERR, "Failed to start phy timer\n"); }