From patchwork Thu Apr 27 06:19:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126595 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1290642A08; Thu, 27 Apr 2023 08:40:55 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 383D04300E; Thu, 27 Apr 2023 08:38:37 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 129CB42FF2 for ; Thu, 27 Apr 2023 08:38:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682577515; x=1714113515; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FAs8M5VxU+bGxECfHE3AswCJ/rmCPxXPTOdphycIZvE=; b=D4jKz2wt0IX6Va+AEOpXc1j4lpLxOJtY/c00sCK+ZtnaFYZTQQVTYm6D d2RdkPP02HtTVbfZ21jogY7OtbRbg4HKSEXfDods/lf6wj0bP+8Teq6O9 zf6HoeoPnqnEP1Psjr9n6g2pR/Y5KsKLJsTGt0/T+daXN+Qz5uX4m1d32 1IfXJQM+QSiBetfmMbjNeH56OfN+nUp0s0aNyUqPMJoIvtj2RoedonW8I JJdqndE6Mtn4HU9ZA5B9mgA4UaC3gNqT778/hzPK4ufqyB/ObRxajNlfg sOIc0tTupk2GSdOqd5Ym3YMDzeNIHDXYi1B4U/m3vyBxs7XEJNZr6A43E Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="375324410" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324410" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:38:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845887" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845887" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:32 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Lukasz Plachno Subject: [PATCH 28/30] net/ice/base: use const array to store link modes Date: Thu, 27 Apr 2023 06:19:59 +0000 Message-Id: <20230427062001.478032-29-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Change suggested during review on E1000 mailing list. Implementation moves 1,5k of .text to .rodata Signed-off-by: Lukasz Plachno Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_common.c | 135 +++++++----------------------- 1 file changed, 30 insertions(+), 105 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index e4b25321db..f899e4644c 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -85,118 +85,36 @@ static const char * const ice_link_mode_str_high[] = { ice_arr_elem_idx(3, "100G_AUI2_AOC_ACC"), ice_arr_elem_idx(4, "100G_AUI2"), }; -/** - * dump_phy_type - helper function that prints PHY type strings - * @hw: pointer to the HW structure - * @phy: 64 bit PHY type to decipher - * @i: bit index within phy - * @phy_string: string corresponding to bit i in phy - * @prefix: prefix string to differentiate multiple dumps - */ -static void -dump_phy_type(struct ice_hw *hw, u64 phy, u8 i, const char *phy_string, - const char *prefix) -{ - if (phy & BIT_ULL(i)) - ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", prefix, i, - phy_string); -} /** - * ice_dump_phy_type_low - helper function to dump phy_type_low + * ice_dump_phy_type - helper function to dump phy_type * @hw: pointer to the HW structure * @low: 64 bit value for phy_type_low + * @high: 64 bit value for phy_type_high * @prefix: prefix string to differentiate multiple dumps */ static void -ice_dump_phy_type_low(struct ice_hw *hw, u64 low, const char *prefix) +ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix) { + u32 i; + ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, (unsigned long long)low); - dump_phy_type(hw, low, 0, "100BASE_TX", prefix); - dump_phy_type(hw, low, 1, "100M_SGMII", prefix); - dump_phy_type(hw, low, 2, "1000BASE_T", prefix); - dump_phy_type(hw, low, 3, "1000BASE_SX", prefix); - dump_phy_type(hw, low, 4, "1000BASE_LX", prefix); - dump_phy_type(hw, low, 5, "1000BASE_KX", prefix); - dump_phy_type(hw, low, 6, "1G_SGMII", prefix); - dump_phy_type(hw, low, 7, "2500BASE_T", prefix); - dump_phy_type(hw, low, 8, "2500BASE_X", prefix); - dump_phy_type(hw, low, 9, "2500BASE_KX", prefix); - dump_phy_type(hw, low, 10, "5GBASE_T", prefix); - dump_phy_type(hw, low, 11, "5GBASE_KR", prefix); - dump_phy_type(hw, low, 12, "10GBASE_T", prefix); - dump_phy_type(hw, low, 13, "10G_SFI_DA", prefix); - dump_phy_type(hw, low, 14, "10GBASE_SR", prefix); - dump_phy_type(hw, low, 15, "10GBASE_LR", prefix); - dump_phy_type(hw, low, 16, "10GBASE_KR_CR1", prefix); - dump_phy_type(hw, low, 17, "10G_SFI_AOC_ACC", prefix); - dump_phy_type(hw, low, 18, "10G_SFI_C2C", prefix); - dump_phy_type(hw, low, 19, "25GBASE_T", prefix); - dump_phy_type(hw, low, 20, "25GBASE_CR", prefix); - dump_phy_type(hw, low, 21, "25GBASE_CR_S", prefix); - dump_phy_type(hw, low, 22, "25GBASE_CR1", prefix); - dump_phy_type(hw, low, 23, "25GBASE_SR", prefix); - dump_phy_type(hw, low, 24, "25GBASE_LR", prefix); - dump_phy_type(hw, low, 25, "25GBASE_KR", prefix); - dump_phy_type(hw, low, 26, "25GBASE_KR_S", prefix); - dump_phy_type(hw, low, 27, "25GBASE_KR1", prefix); - dump_phy_type(hw, low, 28, "25G_AUI_AOC_ACC", prefix); - dump_phy_type(hw, low, 29, "25G_AUI_C2C", prefix); - dump_phy_type(hw, low, 30, "40GBASE_CR4", prefix); - dump_phy_type(hw, low, 31, "40GBASE_SR4", prefix); - dump_phy_type(hw, low, 32, "40GBASE_LR4", prefix); - dump_phy_type(hw, low, 33, "40GBASE_KR4", prefix); - dump_phy_type(hw, low, 34, "40G_XLAUI_AOC_ACC", prefix); - dump_phy_type(hw, low, 35, "40G_XLAUI", prefix); - dump_phy_type(hw, low, 36, "50GBASE_CR2", prefix); - dump_phy_type(hw, low, 37, "50GBASE_SR2", prefix); - dump_phy_type(hw, low, 38, "50GBASE_LR2", prefix); - dump_phy_type(hw, low, 39, "50GBASE_KR2", prefix); - dump_phy_type(hw, low, 40, "50G_LAUI2_AOC_ACC", prefix); - dump_phy_type(hw, low, 41, "50G_LAUI2", prefix); - dump_phy_type(hw, low, 42, "50G_AUI2_AOC_ACC", prefix); - dump_phy_type(hw, low, 43, "50G_AUI2", prefix); - dump_phy_type(hw, low, 44, "50GBASE_CP", prefix); - dump_phy_type(hw, low, 45, "50GBASE_SR", prefix); - dump_phy_type(hw, low, 46, "50GBASE_FR", prefix); - dump_phy_type(hw, low, 47, "50GBASE_LR", prefix); - dump_phy_type(hw, low, 48, "50GBASE_KR_PAM4", prefix); - dump_phy_type(hw, low, 49, "50G_AUI1_AOC_ACC", prefix); - dump_phy_type(hw, low, 50, "50G_AUI1", prefix); - dump_phy_type(hw, low, 51, "100GBASE_CR4", prefix); - dump_phy_type(hw, low, 52, "100GBASE_SR4", prefix); - dump_phy_type(hw, low, 53, "100GBASE_LR4", prefix); - dump_phy_type(hw, low, 54, "100GBASE_KR4", prefix); - dump_phy_type(hw, low, 55, "100G_CAUI4_AOC_ACC", prefix); - dump_phy_type(hw, low, 56, "100G_CAUI4", prefix); - dump_phy_type(hw, low, 57, "100G_AUI4_AOC_ACC", prefix); - dump_phy_type(hw, low, 58, "100G_AUI4", prefix); - dump_phy_type(hw, low, 59, "100GBASE_CR_PAM4", prefix); - dump_phy_type(hw, low, 60, "100GBASE_KR_PAM4", prefix); - dump_phy_type(hw, low, 61, "100GBASE_CP2", prefix); - dump_phy_type(hw, low, 62, "100GBASE_SR2", prefix); - dump_phy_type(hw, low, 63, "100GBASE_DR", prefix); -} - -/** - * ice_dump_phy_type_high - helper function to dump phy_type_high - * @hw: pointer to the HW structure - * @high: 64 bit value for phy_type_high - * @prefix: prefix string to differentiate multiple dumps - */ -static void -ice_dump_phy_type_high(struct ice_hw *hw, u64 high, const char *prefix) -{ + for (i = 0; i < ARRAY_SIZE(ice_link_mode_str_low); i++) { + if (low & BIT_ULL(i)) + ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", + prefix, i, ice_link_mode_str_low[i]); + } + ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, (unsigned long long)high); - dump_phy_type(hw, high, 0, "100GBASE_KR2_PAM4", prefix); - dump_phy_type(hw, high, 1, "100G_CAUI2_AOC_ACC", prefix); - dump_phy_type(hw, high, 2, "100G_CAUI2", prefix); - dump_phy_type(hw, high, 3, "100G_AUI2_AOC_ACC", prefix); - dump_phy_type(hw, high, 4, "100G_AUI2", prefix); + for (i = 0; i < ARRAY_SIZE(ice_link_mode_str_high); i++) { + if (high & BIT_ULL(i)) + ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", + prefix, i, ice_link_mode_str_high[i]); + } } /** @@ -551,23 +469,30 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM); cmd->param0 |= CPU_TO_LE16(report_mode); + status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n"); - if (report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) + switch (report_mode) { + case ICE_AQC_REPORT_TOPO_CAP_MEDIA: prefix = "phy_caps_media"; - else if (report_mode == ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA) + break; + case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA: prefix = "phy_caps_no_media"; - else if (report_mode == ICE_AQC_REPORT_ACTIVE_CFG) + break; + case ICE_AQC_REPORT_ACTIVE_CFG: prefix = "phy_caps_active"; - else if (report_mode == ICE_AQC_REPORT_DFLT_CFG) + break; + case ICE_AQC_REPORT_DFLT_CFG: prefix = "phy_caps_default"; - else + break; + default: prefix = "phy_caps_invalid"; + } - ice_dump_phy_type_low(hw, LE64_TO_CPU(pcaps->phy_type_low), prefix); - ice_dump_phy_type_high(hw, LE64_TO_CPU(pcaps->phy_type_high), prefix); + ice_dump_phy_type(hw, LE64_TO_CPU(pcaps->phy_type_low), + LE64_TO_CPU(pcaps->phy_type_high), prefix); ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n", prefix, report_mode);