From patchwork Thu Apr 27 06:20:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126597 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B975442A08; Thu, 27 Apr 2023 08:41:06 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 095C34301A; Thu, 27 Apr 2023 08:38:41 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 3904E42DB8; Thu, 27 Apr 2023 08:38:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682577518; x=1714113518; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=maqANsBilWmahHiq04uLYfoc3tmCUU3mkjNx/8z8ICs=; b=AiCkM0lYK6LdgXn/5KyHO8TKp48OhYTs9IosinpcUpqHMp6KC++v4a4y uY9xu8qQxD+Djj5TUvYhG4Lk4WklOHL9TcXeCGMg9amiIEgQHMNNiq2bu NUzQGswovYqWv1gjVIs/6P5xOqMO6yAi332B2CV5wPaGOBnHN4htfHzog U20xKWclCTXpd2t1HUchXGxvQcmMxreeF7ZKUpyAJDrEoTOkFZtllakRS VWtEco/kK9qiCENqtpZd1mDLFXonEapDbOdfVLO0X0bHsnNq+f+ulvIOm b3rtle239wd3YVsGAufY+UWx7yvgBeP+v8KKA/sw49aUI4e7dPxxL4CF4 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="375324418" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324418" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:38:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845900" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845900" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:35 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , stable@dpdk.org, Paul Greenwalt Subject: [PATCH 30/30] net/ice/base: fix Generic Checksum acronym Date: Thu, 27 Apr 2023 06:20:01 +0000 Message-Id: <20230427062001.478032-31-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fixes: c31095a0b20f ("net/ice/base: add GCO defines and GCO flex descriptor") Cc: stable@dpdk.org Signed-off-by: Paul Greenwalt Signed-off-by: Qiming Yang Signed-off-by: Paul Greenwalt Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_common.c | 2 +- drivers/net/ice/base/ice_lan_tx_rx.h | 15 ++++++++------- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 7d2a254c47..c324500b54 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -1488,7 +1488,7 @@ const struct ice_ctx_ele ice_tlan_ctx_info[] = { ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), - ICE_CTX_STORE(ice_tlan_ctx, gsc_ena, 1, 172), + ICE_CTX_STORE(ice_tlan_ctx, gcs_ena, 1, 172), { 0 } }; diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h index d8ac841e46..d84f2f6db5 100644 --- a/drivers/net/ice/base/ice_lan_tx_rx.h +++ b/drivers/net/ice/base/ice_lan_tx_rx.h @@ -747,7 +747,7 @@ enum ice_rxdid { ICE_RXDID_FLEX_NIC = 2, ICE_RXDID_FLEX_NIC_2 = 6, ICE_RXDID_HW = 7, - ICE_RXDID_GSC = 9, + ICE_RXDID_GCS = 9, ICE_RXDID_COMMS_GENERIC = 16, ICE_RXDID_COMMS_AUX_VLAN = 17, ICE_RXDID_COMMS_AUX_IPV4 = 18, @@ -1069,14 +1069,14 @@ enum ice_tx_desc_len_fields { struct ice_tx_ctx_desc { __le32 tunneling_params; __le16 l2tag2; - __le16 gsc; + __le16 gcs; __le64 qw1; }; -#define ICE_TX_GSC_DESC_START 0 /* 7 BITS */ -#define ICE_TX_GSC_DESC_OFFSET 7 /* 4 BITS */ -#define ICE_TX_GSC_DESC_TYPE 11 /* 2 BITS */ -#define ICE_TX_GSC_DESC_ENA 13 /* 1 BIT */ +#define ICE_TX_GCS_DESC_START 0 /* 7 BITS */ +#define ICE_TX_GCS_DESC_OFFSET 7 /* 4 BITS */ +#define ICE_TX_GCS_DESC_TYPE 11 /* 2 BITS */ +#define ICE_TX_GCS_DESC_ENA 13 /* 1 BIT */ #define ICE_TXD_CTX_QW1_DTYPE_S 0 #define ICE_TXD_CTX_QW1_DTYPE_M (0xFUL << ICE_TXD_CTX_QW1_DTYPE_S) @@ -1188,8 +1188,9 @@ struct ice_tlan_ctx { u8 drop_ena; u8 cache_prof_idx; u8 pkt_shaper_prof_idx; - u8 gsc_ena; + u8 gcs_ena; u8 int_q_state; /* width not needed - internal - DO NOT WRITE!!! */ + u16 tail; }; /* LAN Tx Completion Queue data */