From patchwork Thu Apr 27 06:19:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126571 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C735A42A08; Thu, 27 Apr 2023 08:38:19 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 09D2C42D5E; Thu, 27 Apr 2023 08:37:55 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id EC3DF42D2D for ; Thu, 27 Apr 2023 08:37:52 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682577473; x=1714113473; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gWentlx+9rzeM7saZOVSLmbcup++26Q6uwOVK0rP5aE=; b=XuCBpqA86Pw89qaNgQ/K1UGI5tJrmMeBb5chROGrhB73wESOq8Kx8ySe +S60M5LF+G7wBBDOYizN1xdrC6zbMix4QeA5NCCuwevGHAO9qX1unFBiO gxzJ4dx47fSWwIkZ2YzEuQMmntWu6OMyfnbUk58zoj94usoofmy94QLaY KVEkvHUTqQsnhr63S+sA6bZN5gZ4oMXDoEDtXrvCO8OwwaJACkHNdlOvH M3elux7LT9uaw6+Ent4pJt8mT1fDJrkwjsgK31tFeREhMOy6bU86CFQHw iLHhlKD6g3aKS7JCU13V/yZoSvo5gCjfUlSfTizIAzImyuLgRugSpCxId w==; X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="375324269" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324269" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:37:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845673" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845673" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:37:49 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Ashish Shah Subject: [PATCH 04/30] net/ice/base: update flow seg fields to declared bitmaps Date: Thu, 27 Apr 2023 06:19:35 +0000 Message-Id: <20230427062001.478032-5-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org ice_flow_seg_info fields match and range are being used with bit operations but not declared as bitmaps. This can cause issues when casting values greater than 32. This change is to declare them as proper bitmaps so that the bitmap operations can function as intended. Signed-off-by: Ashish Shah Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_flow.c | 74 +++++++++++++++++++++++---------- drivers/net/ice/base/ice_flow.h | 6 ++- 2 files changed, 56 insertions(+), 24 deletions(-) diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index 5254ee27ed..8db394471c 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -1132,6 +1132,7 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params) ice_and_bitmap(params->ptypes, params->ptypes, src, ICE_FLOW_PTYPE_MAX); } + if ((hdrs & ICE_FLOW_SEG_HDR_IPV4) && (hdrs & ICE_FLOW_SEG_HDR_IPV_OTHER)) { src = i ? @@ -1371,7 +1372,7 @@ ice_flow_xtract_pkt_flags(struct ice_hw *hw, */ static enum ice_status ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params, - u8 seg, enum ice_flow_field fld, u64 match) + u8 seg, enum ice_flow_field fld, ice_bitmap_t *match) { enum ice_flow_field sib = ICE_FLOW_FIELD_IDX_MAX; u8 fv_words = (u8)hw->blk[params->blk].es.fvw; @@ -1420,7 +1421,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params, /* If the sibling field is also included, that field's * mask needs to be included. */ - if (match & BIT(sib)) + if (ice_is_bit_set(match, sib)) sib_mask = ice_flds_info[sib].mask; break; case ICE_FLOW_FIELD_IDX_IPV6_TTL: @@ -1451,7 +1452,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params, /* If the sibling field is also included, that field's * mask needs to be included. */ - if (match & BIT(sib)) + if (ice_is_bit_set(match, sib)) sib_mask = ice_flds_info[sib].mask; break; case ICE_FLOW_FIELD_IDX_IPV4_SA: @@ -1722,15 +1723,16 @@ ice_flow_create_xtrct_seq(struct ice_hw *hw, } for (i = 0; i < params->prof->segs_cnt; i++) { - u64 match = params->prof->segs[i].match; + ice_declare_bitmap(match, ICE_FLOW_FIELD_IDX_MAX); enum ice_flow_field j; - ice_for_each_set_bit(j, (ice_bitmap_t *)&match, - ICE_FLOW_FIELD_IDX_MAX) { + ice_cp_bitmap(match, params->prof->segs[i].match, + ICE_FLOW_FIELD_IDX_MAX); + ice_for_each_set_bit(j, match, ICE_FLOW_FIELD_IDX_MAX) { status = ice_flow_xtract_fld(hw, params, i, j, match); if (status) return status; - ice_clear_bit(j, (ice_bitmap_t *)&match); + ice_clear_bit(j, match); } /* Process raw matching bytes */ @@ -1789,7 +1791,7 @@ ice_flow_acl_def_entry_frmt(struct ice_flow_prof_params *params) struct ice_flow_seg_info *seg = ¶ms->prof->segs[i]; u16 j; - ice_for_each_set_bit(j, (ice_bitmap_t *)&seg->match, + ice_for_each_set_bit(j, seg->match, (u16)ICE_FLOW_FIELD_IDX_MAX) { struct ice_flow_fld_info *fld = &seg->fields[j]; @@ -1932,7 +1934,10 @@ ice_flow_find_prof_conds(struct ice_hw *hw, enum ice_block blk, for (i = 0; i < segs_cnt; i++) if (segs[i].hdrs != p->segs[i].hdrs || ((conds & ICE_FLOW_FIND_PROF_CHK_FLDS) && - segs[i].match != p->segs[i].match)) + (ice_cmp_bitmap(segs[i].match, + p->segs[i].match, + ICE_FLOW_FIELD_IDX_MAX) == + false))) break; /* A match is found if all segments are matched */ @@ -2432,7 +2437,7 @@ ice_flow_acl_set_xtrct_seq(struct ice_hw *hw, struct ice_flow_prof *prof) struct ice_flow_seg_info *seg = &prof->segs[i]; u16 j; - ice_for_each_set_bit(j, (ice_bitmap_t *)&seg->match, + ice_for_each_set_bit(j, seg->match, ICE_FLOW_FIELD_IDX_MAX) { info = &seg->fields[j]; @@ -2601,7 +2606,8 @@ ice_flow_set_hw_prof(struct ice_hw *hw, u16 dest_vsi_handle, idx = i; params->es[idx].prot_id = prof->fv[i].proto_id; params->es[idx].off = prof->fv[i].offset; - params->mask[idx] = CPU_TO_BE16(prof->fv[i].msk); + params->mask[idx] = (((prof->fv[i].msk) << 8) & 0xff00) | + (((prof->fv[i].msk) >> 8) & 0x00ff); } switch (prof->flags) { @@ -3002,7 +3008,7 @@ ice_flow_acl_frmt_entry(struct ice_hw *hw, struct ice_flow_prof *prof, struct ice_flow_seg_info *seg = &prof->segs[i]; u16 j; - ice_for_each_set_bit(j, (ice_bitmap_t *)&seg->match, + ice_for_each_set_bit(j, seg->match, (u16)ICE_FLOW_FIELD_IDX_MAX) { struct ice_flow_fld_info *info = &seg->fields[j]; @@ -3534,7 +3540,7 @@ enum ice_status ice_flow_rem_entry(struct ice_hw *hw, enum ice_block blk, if (entry_h == ICE_FLOW_ENTRY_HANDLE_INVAL) return ICE_ERR_PARAM; - entry = ICE_FLOW_ENTRY_PTR((intptr_t)entry_h); + entry = ICE_FLOW_ENTRY_PTR(entry_h); /* Retain the pointer to the flow profile as the entry will be freed */ prof = entry->prof; @@ -3576,11 +3582,9 @@ ice_flow_set_fld_ext(struct ice_flow_seg_info *seg, enum ice_flow_field fld, enum ice_flow_fld_match_type field_type, u16 val_loc, u16 mask_loc, u16 last_loc) { - u64 bit = BIT_ULL(fld); - - seg->match |= bit; + ice_set_bit(fld, seg->match); if (field_type == ICE_FLOW_FLD_TYPE_RANGE) - seg->range |= bit; + ice_set_bit(fld, seg->range); seg->fields[fld].type = field_type; seg->fields[fld].src.val = val_loc; @@ -3741,7 +3745,7 @@ enum ice_status ice_flow_rem_vsi_prof(struct ice_hw *hw, enum ice_block blk, u16 } #define ICE_FLOW_RSS_SEG_HDR_L2_MASKS \ -(ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_ETH_NON_IP | ICE_FLOW_SEG_HDR_VLAN) +(ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_VLAN) #define ICE_FLOW_RSS_SEG_HDR_L3_MASKS \ (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6) @@ -3856,6 +3860,7 @@ enum ice_status ice_rem_vsi_rss_cfg(struct ice_hw *hw, u16 vsi_handle) const enum ice_block blk = ICE_BLK_RSS; struct ice_flow_prof *p, *t; enum ice_status status = ICE_SUCCESS; + u16 vsig; if (!ice_is_vsi_valid(hw, vsi_handle)) return ICE_ERR_PARAM; @@ -3865,7 +3870,16 @@ enum ice_status ice_rem_vsi_rss_cfg(struct ice_hw *hw, u16 vsi_handle) ice_acquire_lock(&hw->rss_locks); LIST_FOR_EACH_ENTRY_SAFE(p, t, &hw->fl_profs[blk], ice_flow_prof, - l_entry) + l_entry) { + int ret; + + /* check if vsig is already removed */ + ret = ice_vsig_find_vsi(hw, blk, + ice_get_hw_vsi_num(hw, vsi_handle), + &vsig); + if (!ret && !vsig) + break; + if (ice_is_bit_set(p->vsis, vsi_handle)) { status = ice_flow_disassoc_prof(hw, blk, p, vsi_handle); if (status) @@ -3877,6 +3891,7 @@ enum ice_status ice_rem_vsi_rss_cfg(struct ice_hw *hw, u16 vsi_handle) break; } } + } ice_release_lock(&hw->rss_locks); return status; @@ -3918,6 +3933,14 @@ ice_rem_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof) { enum ice_rss_cfg_hdr_type hdr_type; struct ice_rss_cfg *r, *tmp; + u64 seg_match = 0; + u16 i; + + /* convert match bitmap to u64 for hash field comparison */ + ice_for_each_set_bit(i, prof->segs[prof->segs_cnt - 1].match, + ICE_FLOW_FIELD_IDX_MAX) { + seg_match |= 1ULL << i; + } /* Search for RSS hash fields associated to the VSI that match the * hash configurations associated to the flow profile. If found @@ -3926,7 +3949,7 @@ ice_rem_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof) hdr_type = ice_get_rss_hdr_type(prof); LIST_FOR_EACH_ENTRY_SAFE(r, tmp, &hw->rss_list_head, ice_rss_cfg, l_entry) - if (r->hash.hash_flds == prof->segs[prof->segs_cnt - 1].match && + if (r->hash.hash_flds == seg_match && r->hash.addl_hdrs == prof->segs[prof->segs_cnt - 1].hdrs && r->hash.hdr_type == hdr_type) { ice_clear_bit(vsi_handle, r->vsis); @@ -3951,11 +3974,18 @@ ice_add_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof) { enum ice_rss_cfg_hdr_type hdr_type; struct ice_rss_cfg *r, *rss_cfg; + u64 seg_match = 0; + u16 i; + + ice_for_each_set_bit(i, prof->segs[prof->segs_cnt - 1].match, + ICE_FLOW_FIELD_IDX_MAX) { + seg_match |= 1ULL << i; + } hdr_type = ice_get_rss_hdr_type(prof); LIST_FOR_EACH_ENTRY(r, &hw->rss_list_head, ice_rss_cfg, l_entry) - if (r->hash.hash_flds == prof->segs[prof->segs_cnt - 1].match && + if (r->hash.hash_flds == seg_match && r->hash.addl_hdrs == prof->segs[prof->segs_cnt - 1].hdrs && r->hash.hdr_type == hdr_type) { ice_set_bit(vsi_handle, r->vsis); @@ -3966,7 +3996,7 @@ ice_add_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof) if (!rss_cfg) return ICE_ERR_NO_MEMORY; - rss_cfg->hash.hash_flds = prof->segs[prof->segs_cnt - 1].match; + rss_cfg->hash.hash_flds = seg_match; rss_cfg->hash.addl_hdrs = prof->segs[prof->segs_cnt - 1].hdrs; rss_cfg->hash.hdr_type = hdr_type; rss_cfg->hash.symm = prof->cfg.symm; diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h index 57e8e1f1df..1415f5ba87 100644 --- a/drivers/net/ice/base/ice_flow.h +++ b/drivers/net/ice/base/ice_flow.h @@ -452,8 +452,10 @@ struct ice_flow_seg_fld_raw { struct ice_flow_seg_info { u32 hdrs; /* Bitmask indicating protocol headers present */ - u64 match; /* Bitmask indicating header fields to be matched */ - u64 range; /* Bitmask indicating header fields matched as ranges */ + /* Bitmask indicating header fields to be matched */ + ice_declare_bitmap(match, ICE_FLOW_FIELD_IDX_MAX); + /* Bitmask indicating header fields matched as ranges */ + ice_declare_bitmap(range, ICE_FLOW_FIELD_IDX_MAX); struct ice_flow_fld_info fields[ICE_FLOW_FIELD_IDX_MAX];