From patchwork Thu Apr 27 06:19:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126573 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A0E3C42A08; Thu, 27 Apr 2023 08:38:39 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 342BD42D6C; Thu, 27 Apr 2023 08:37:59 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 6851542D46 for ; Thu, 27 Apr 2023 08:37:56 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682577476; x=1714113476; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pADcOzUlbE8snxSSeTZx+QfLpkAHximSLLEIHUADapQ=; b=OoZfeMUvWlWJzCvJj1dtkqAWBFkvhivNQRBnQcXGgBPtJXp2Z9XOv1yP v/KaljhAPtbVVkmCTJZ6rVVJyvd4G4guT8fDz/gJ0HCea04ADqCa/fbrp awOmg0hhq25qa1vbgrB4qKyL2dzQsP737E7IzzokUk7N0YAT4F1QlnIak 2Wreu/jnVQ5xGSthc037gKb6RQAaLYIgaPPCNkb5qAC05KSssQjdf+V0H HkyLKvBxYRz0jkZFIDcbbR8eGmkHUe0eDa5NOKQGsQ6VND6MieNwQcddd dKQeWQoRGeGU4djCkDgIRgwzdGu/km2/EIUJBu7wS4rjft6mg61qJ+Ye4 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="375324282" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324282" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:37:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845689" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845689" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:37:53 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Zhirun Yan Subject: [PATCH 06/30] net/ice/base: add ability to set markid via switch filter Date: Thu, 27 Apr 2023 06:19:37 +0000 Message-Id: <20230427062001.478032-7-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Support to add large action to set 32 bits markid via switch filter. For OVS-DPDK VXLAN acceleration solution, switch markid will be used for mega flow match for decap. For one ptype, the pattern may have different fields as follow: eth / ipv4 src / udp dst eth / ipv4 dst src / udp dst FDIR will have conflict with the same profile id. So we could chose switch to set markid. Signed-off-by: Zhirun Yan Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_common.c | 17 ++++++++++- drivers/net/ice/base/ice_sched.c | 2 +- drivers/net/ice/base/ice_switch.c | 48 +++++++++++++++++++++++++++---- drivers/net/ice/base/ice_switch.h | 26 +++++++++-------- drivers/net/ice/base/ice_type.h | 3 ++ 5 files changed, 77 insertions(+), 19 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 006ffa802c..5bd40ece78 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -2369,6 +2369,11 @@ ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, true : false; ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, caps->nvm_unified_update); + caps->netlist_auth = + (number & ICE_NVM_MGMT_NETLIST_AUTH_SUPPORT) ? + true : false; + ice_debug(hw, ICE_DBG_INIT, "%s: netlist_auth = %d\n", prefix, + caps->netlist_auth); break; case ICE_AQC_CAPS_MAX_MTU: caps->max_mtu = number; @@ -3814,6 +3819,7 @@ enum ice_status ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, struct ice_sq_cd *cd) { + enum ice_status status = ICE_ERR_AQ_ERROR; struct ice_aqc_restart_an *cmd; struct ice_aq_desc desc; @@ -3828,7 +3834,16 @@ ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, else cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; - return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); + status = ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); + if (status) + return status; + + if (ena_link) + pi->phy.curr_user_phy_cfg.caps |= ICE_AQC_PHY_EN_LINK; + else + pi->phy.curr_user_phy_cfg.caps &= ~ICE_AQC_PHY_EN_LINK; + + return ICE_SUCCESS; } /** diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c index 83cd152388..e3a638dcdd 100644 --- a/drivers/net/ice/base/ice_sched.c +++ b/drivers/net/ice/base/ice_sched.c @@ -1057,11 +1057,11 @@ ice_sched_add_nodes_to_layer(struct ice_port_info *pi, u32 *first_teid_ptr = first_node_teid; u16 new_num_nodes = num_nodes; enum ice_status status = ICE_SUCCESS; + u32 temp; *num_nodes_added = 0; while (*num_nodes_added < num_nodes) { u16 max_child_nodes, num_added = 0; - u32 temp; status = ice_sched_add_nodes_to_hw_layer(pi, tc_node, parent, layer, new_num_nodes, diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 31fec80735..dd4cc38114 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -2520,7 +2520,7 @@ ice_free_sw_marker_lg(struct ice_hw *hw, u16 marker_lg_id, u32 sw_marker) return ICE_ERR_NO_MEMORY; sw_buf->num_elems = CPU_TO_LE16(num_elems); - if (sw_marker == (sw_marker & 0xFFFF)) + if (sw_marker <= 0xFFFF) sw_buf->res_type = CPU_TO_LE16(ICE_AQC_RES_TYPE_WIDE_TABLE_1); else sw_buf->res_type = CPU_TO_LE16(ICE_AQC_RES_TYPE_WIDE_TABLE_2); @@ -4299,9 +4299,9 @@ enum ice_status ice_update_sw_rule_bridge_mode(struct ice_hw *hw) { struct ice_fltr_mgmt_list_entry *fm_entry; enum ice_status status = ICE_SUCCESS; + struct ice_switch_info *sw = NULL; struct LIST_HEAD_TYPE *rule_head; struct ice_lock *rule_lock; /* Lock to protect filter rule list */ - struct ice_switch_info *sw; sw = hw->switch_info; rule_lock = &sw->recp_list[ICE_SW_LKUP_MAC].filt_rule_lock; @@ -5545,7 +5545,7 @@ ice_cfg_dflt_vsi(struct ice_port_info *pi, u16 vsi_handle, bool set, u8 direction) { struct ice_fltr_list_entry f_list_entry; - struct ice_sw_recipe *recp_list; + struct ice_sw_recipe *recp_list = NULL; struct ice_fltr_info f_info; struct ice_hw *hw = pi->hw; enum ice_status status; @@ -8698,6 +8698,36 @@ ice_fill_adv_packet_tun(struct ice_hw *hw, enum ice_sw_tunnel_type tun_type, return ICE_ERR_CFG; } +/** + * ice_fill_adv_packet_vlan - fill dummy packet with VLAN tag type + * @vlan_type: VLAN tag type + * @pkt: dummy packet to fill in + * @offsets: offset info for the dummy packet + */ +static enum ice_status +ice_fill_adv_packet_vlan(u16 vlan_type, u8 *pkt, + const struct ice_dummy_pkt_offsets *offsets) +{ + u16 i; + + /* Find VLAN header and insert VLAN TPID */ + for (i = 0; offsets[i].type != ICE_PROTOCOL_LAST; i++) { + if (offsets[i].type == ICE_VLAN_OFOS || + offsets[i].type == ICE_VLAN_EX) { + struct ice_vlan_hdr *hdr; + u16 offset; + + offset = offsets[i].offset; + hdr = (struct ice_vlan_hdr *)&pkt[offset]; + hdr->type = CPU_TO_BE16(vlan_type); + + return ICE_SUCCESS; + } + } + + return ICE_ERR_CFG; +} + /** * ice_find_adv_rule_entry - Search a rule entry * @hw: pointer to the hardware structure @@ -9131,7 +9161,7 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, ICE_SINGLE_ACT_Q_REGION_M; break; case ICE_SET_MARK: - if (rinfo->sw_act.markid != (rinfo->sw_act.markid & 0xFFFF)) + if (rinfo->sw_act.markid > 0xFFFF) nb_lg_acts_mark += 1; /* Allocate a hardware table entry to hold large act. */ status = ice_alloc_res_lg_act(hw, &lg_act_id, nb_lg_acts_mark); @@ -9184,6 +9214,14 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, goto err_ice_add_adv_rule; } + if (rinfo->vlan_type != 0 && ice_is_dvm_ena(hw)) { + status = ice_fill_adv_packet_vlan(rinfo->vlan_type, + s_rule->hdr_data, + pkt_offsets); + if (status) + goto err_ice_add_adv_rule; + } + rx_tx = s_rule; if (rinfo->sw_act.fltr_act == ICE_SET_MARK) { lg_act_sz = (u16)ice_struct_size(lg_rule, act, nb_lg_acts_mark); @@ -9752,7 +9790,7 @@ enum ice_status ice_replay_vsi_all_fltr(struct ice_hw *hw, struct ice_port_info *pi, u16 vsi_handle) { - struct ice_switch_info *sw; + struct ice_switch_info *sw = NULL; enum ice_status status; u8 i; diff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h index c55ef19a8c..49bd535c79 100644 --- a/drivers/net/ice/base/ice_switch.h +++ b/drivers/net/ice/base/ice_switch.h @@ -207,19 +207,19 @@ struct ice_adv_lkup_elem { union ice_prot_hdr m_u; /* Mask of header values to match */ }; -struct lg_entry_vsi_fwd { +struct entry_vsi_fwd { u16 vsi_list; u8 list; u8 valid; }; -struct lg_entry_to_q { +struct entry_to_q { u16 q_idx; u8 q_region_sz; u8 q_pri; }; -struct lg_entry_prune { +struct entry_prune { u16 vsi_list; u8 list; u8 egr; @@ -227,28 +227,29 @@ struct lg_entry_prune { u8 prune_t; }; -struct lg_entry_mirror { +struct entry_mirror { u16 mirror_vsi; }; -struct lg_entry_generic_act { +struct entry_generic_act { u16 generic_value; u8 offset; u8 priority; }; -struct lg_entry_statistics { +struct entry_statistics { u8 counter_idx; }; union lg_act_entry { - struct lg_entry_vsi_fwd vsi_fwd; - struct lg_entry_to_q to_q; - struct lg_entry_prune prune; - struct lg_entry_mirror mirror; - struct lg_entry_generic_act generic_act; - struct lg_entry_statistics statistics; + struct entry_vsi_fwd vsi_fwd; + struct entry_to_q to_q; + struct entry_prune prune; + struct entry_mirror mirror; + struct entry_generic_act generic_act; + struct entry_statistics statistics; }; + struct ice_prof_type_entry { u16 prof_id; enum ice_sw_tunnel_type type; @@ -301,6 +302,7 @@ struct ice_adv_rule_info { u8 rx; /* true means LOOKUP_RX otherwise LOOKUP_TX */ u16 fltr_rule_id; u16 lg_id; + u16 vlan_type; struct ice_adv_rule_flags_info flags_info; }; diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index 3249e359de..b2df99e472 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -693,9 +693,11 @@ struct ice_hw_common_caps { bool sec_rev_disabled; bool update_disabled; bool nvm_unified_update; + bool netlist_auth; #define ICE_NVM_MGMT_SEC_REV_DISABLED BIT(0) #define ICE_NVM_MGMT_UPDATE_DISABLED BIT(1) #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3) +#define ICE_NVM_MGMT_NETLIST_AUTH_SUPPORT BIT(5) /* PCIe reset avoidance */ bool pcie_reset_avoidance; /* false: not supported, true: supported */ /* Post update reset restriction */ @@ -1458,6 +1460,7 @@ enum ice_sw_fwd_act_type { ICE_FWD_TO_QGRP, ICE_SET_MARK, ICE_DROP_PACKET, + ICE_LG_ACTION, ICE_INVAL_ACT };