From patchwork Thu Jun 15 13:09:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 128744 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3226C42CC6; Thu, 15 Jun 2023 15:10:02 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B853540EE3; Thu, 15 Jun 2023 15:10:01 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 159A640E0F for ; Thu, 15 Jun 2023 15:10:00 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35FBB1n6002209 for ; Thu, 15 Jun 2023 06:10:00 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=VtyurhUyMV+BCbVrZyDLPeDj06c75loKxaHR5/d3PRk=; b=Sl2AI0CvWLjGIC7CJo+xkxQudBSP9Jt0h+rkNoyCAOEr9WD0m5lOVf7AD+KPgkpAu1J5 FEbyTZSuA0zvm5OSipmX0d7gLMAFaTxVnBxgvG8rzuiYfQxwSrWqy0k+/nw3nfExGpDJ yhvYXj9JH8cQ/A2dG3ktRu66Ff607Y/n/sOpLCb2uruB2pa38vav/fDtLP/zncK1SCN4 RDi4U+7rHEjW6NAZqD0vHfMhJW13zaeGvtKyMh48NFjogGH6ZZ34zy8bphPUKFAxjSTg SZaNhKpUoJk7VnqO19jrFXjtzTwixdwdDRUXspYq41LNScX8QyjW8hG5JoXMKXhOpBD+ iw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3r7ky1u45r-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 15 Jun 2023 06:10:00 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 15 Jun 2023 06:09:32 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 15 Jun 2023 06:09:32 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 4E0373F7089; Thu, 15 Jun 2023 06:09:30 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 2/3] net/cnxk: support backpressure on SPB pool Date: Thu, 15 Jun 2023 18:39:23 +0530 Message-ID: <20230615130924.828208-2-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230615130924.828208-1-ndabilpuram@marvell.com> References: <20230615130924.828208-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: FzdjNOtaNDy73W4zaXBwQ55YL1qX3nrE X-Proofpoint-ORIG-GUID: FzdjNOtaNDy73W4zaXBwQ55YL1qX3nrE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-15_08,2023-06-14_02,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sunil Kumar Kori With current implementation, backpressure can be configured only on lpb_pool but a RQ can be configured with spb_pool too and spb_pool can also participate to assert backpressure. Enabling backpressure support on spb_pool for 802.3x and 802.1qbb both. Signed-off-by: Sunil Kumar Kori --- drivers/net/cnxk/cnxk_ethdev_ops.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_ethdev_ops.c index da5ee19c85..3ade8eed36 100644 --- a/drivers/net/cnxk/cnxk_ethdev_ops.c +++ b/drivers/net/cnxk/cnxk_ethdev_ops.c @@ -308,7 +308,9 @@ cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev, fc_cfg.rq_cfg.tc = 0; fc_cfg.rq_cfg.rq = rq->qid; fc_cfg.rq_cfg.pool = rq->aura_handle; + fc_cfg.rq_cfg.spb_pool = rq->spb_aura_handle; fc_cfg.rq_cfg.cq_drop = cq->drop_thresh; + fc_cfg.rq_cfg.pool_drop_pct = ROC_NIX_AURA_THRESH; rc = roc_nix_fc_config_set(nix, &fc_cfg); if (rc) @@ -1198,7 +1200,9 @@ nix_priority_flow_ctrl_rq_conf(struct rte_eth_dev *eth_dev, uint16_t qid, fc_cfg.rq_cfg.enable = !!tx_pause; fc_cfg.rq_cfg.rq = rq->qid; fc_cfg.rq_cfg.pool = rxq->qconf.mp->pool_id; + fc_cfg.rq_cfg.spb_pool = rq->spb_aura_handle; fc_cfg.rq_cfg.cq_drop = cq->drop_thresh; + fc_cfg.rq_cfg.pool_drop_pct = ROC_NIX_AURA_THRESH; rc = roc_nix_fc_config_set(nix, &fc_cfg); if (rc) return rc;