From patchwork Wed Jul 12 08:31:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 129496 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9059842E52; Wed, 12 Jul 2023 10:50:03 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9BAE142B8E; Wed, 12 Jul 2023 10:50:00 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id B26A2427EE; Wed, 12 Jul 2023 10:49:57 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689151799; x=1720687799; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1lUAwfe/IJgchFBu0N8bXaeZwmFbfVjcY6RfR5TJwW4=; b=NrkTde/8+a932uEKph32OMi6xD31Hs4eyHEGgiEXiizMXjjyCg7SgcCc P5T/CpIvekGknB9ZO3HRhsnR/KfgvAqd7liqSyP+lnC8iGQ+2zqqF9NUt 58H58JALKkQoYfTckxQRjtNq5m3w74kWmlWdBm8M+ryqaWM3FWSWqVxWn PvS9zn4iAj7wgQtVkgQQOvBWbY2CYGbqcYYXutrq+n2RUiuCyBQrqKw2y n+sUg/d5pm5KrotRnAOA3n/jCHJd/F4DlaOoEbp3dVccZMG4GeCWjfjfm KYnCoDUGkcVD4mfoRadrnEoYAbUh2hxJHWAY+N1aTurVZNBmbnW8aXZ82 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10768"; a="345152458" X-IronPort-AV: E=Sophos;i="6.01,199,1684825200"; d="scan'208";a="345152458" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2023 01:49:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10768"; a="866036713" X-IronPort-AV: E=Sophos;i="6.01,199,1684825200"; d="scan'208";a="866036713" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga001.fm.intel.com with ESMTP; 12 Jul 2023 01:49:32 -0700 From: Qiming Yang To: dev@dpdk.org Cc: beilei.xing@intel.com, qi.z.zhang@intel.com, Qiming Yang , stable@dpdk.org, Mingjin Ye Subject: [PATCH v2 2/3] net/igc: fix Rx and Tx queue status get Date: Wed, 12 Jul 2023 08:31:52 +0000 Message-Id: <20230712083153.3250798-3-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230712083153.3250798-1-qiming.yang@intel.com> References: <20230712083153.3250798-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Igc driver don't enable queue start/stop functions, queue status is not updated when the HW queue enabled or disabled. It caused application can't get correct queue status. This patch fixes the issue by updating the queue states when the queue is disabled or enabled. Fixes: a5aeb2b9e225 ("net/igc: support Rx and Tx") Cc: stable@dpdk.org Signed-off-by: Qiming Yang Signed-off-by: Mingjin Ye --- drivers/net/igc/igc_txrx.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/igc/igc_txrx.c b/drivers/net/igc/igc_txrx.c index c11b6f7f25..5c60e3e997 100644 --- a/drivers/net/igc/igc_txrx.c +++ b/drivers/net/igc/igc_txrx.c @@ -1215,6 +1215,7 @@ igc_rx_init(struct rte_eth_dev *dev) dvmolr |= IGC_DVMOLR_STRCRC; IGC_WRITE_REG(hw, IGC_DVMOLR(rxq->reg_idx), dvmolr); + dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; } return 0; @@ -1888,6 +1889,7 @@ igc_dev_clear_queues(struct rte_eth_dev *dev) if (txq != NULL) { igc_tx_queue_release_mbufs(txq); igc_reset_tx_queue(txq); + dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; } } @@ -1896,6 +1898,7 @@ igc_dev_clear_queues(struct rte_eth_dev *dev) if (rxq != NULL) { igc_rx_queue_release_mbufs(rxq); igc_reset_rx_queue(rxq); + dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; } } } @@ -2143,6 +2146,7 @@ igc_tx_init(struct rte_eth_dev *dev) IGC_TXDCTL_WTHRESH_MSK; txdctl |= IGC_TXDCTL_QUEUE_ENABLE; IGC_WRITE_REG(hw, IGC_TXDCTL(txq->reg_idx), txdctl); + dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; } if (offloads & RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP) {