From patchwork Wed Jul 12 08:31:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 129497 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4E7F742E52; Wed, 12 Jul 2023 10:50:10 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E2C9F42D10; Wed, 12 Jul 2023 10:50:01 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id B7CCC427EE; Wed, 12 Jul 2023 10:49:59 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689151800; x=1720687800; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FyQgBjy3u2SFF2fh87zNXjs/kDMg9ep/LXaDxL1JU2Q=; b=AKA/MRICuefH5RXOfy87J7ToRbI/E+PkvLZ0FKotGY172DpnTYH3/WNe yhNM6jdCtoUYxbITfTICINTJkJorBnL3qruo5QLZpitcH5X2YJUXDiT4B r/JvGHtn2zQcJz/RBp9P5YtJvfMHa5PKT7AKe9w/qnyBLdG9fHKIco1Kp tvF4YglFVADrd1cEH9Tm7wcdyXvro3/db7GO7TEGqSfbgyA/tCMsEkPzz aBEl8ffbWvUFRpxuycjomAZwZSHptS+Oqj42d1UF0J5+Tdbz0igb+y0Fm jr2y9Zucesf35s6IFKtnLcl/1BldnTxEJTK7YaNMHAg9O9j821cXEysNG g==; X-IronPort-AV: E=McAfee;i="6600,9927,10768"; a="345152462" X-IronPort-AV: E=Sophos;i="6.01,199,1684825200"; d="scan'208";a="345152462" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2023 01:49:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10768"; a="866036721" X-IronPort-AV: E=Sophos;i="6.01,199,1684825200"; d="scan'208";a="866036721" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga001.fm.intel.com with ESMTP; 12 Jul 2023 01:49:34 -0700 From: Qiming Yang To: dev@dpdk.org Cc: beilei.xing@intel.com, qi.z.zhang@intel.com, Qiming Yang , stable@dpdk.org, Mingjin Ye Subject: [PATCH v2 3/3] net/e1000: fix Rx and Tx queue status Date: Wed, 12 Jul 2023 08:31:53 +0000 Message-Id: <20230712083153.3250798-4-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230712083153.3250798-1-qiming.yang@intel.com> References: <20230712083153.3250798-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Igb driver don't enable queue start/stop functions, queue status is not updated when the HW queue enabled or disabled. It caused application can't get correct queue status. This patch fixes the issue by updating the queue states when the queue is disabled or enabled. Fixes: be2d648a2dd3 ("igb: add PF support") Cc: stable@dpdk.org Signed-off-by: Qiming Yang Signed-off-by: Mingjin Ye --- drivers/net/e1000/igb_rxtx.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/e1000/igb_rxtx.c b/drivers/net/e1000/igb_rxtx.c index 25ad9eb4e5..61c6394310 100644 --- a/drivers/net/e1000/igb_rxtx.c +++ b/drivers/net/e1000/igb_rxtx.c @@ -1854,6 +1854,7 @@ igb_dev_clear_queues(struct rte_eth_dev *dev) if (txq != NULL) { igb_tx_queue_release_mbufs(txq); igb_reset_tx_queue(txq, dev); + dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; } } @@ -1862,6 +1863,7 @@ igb_dev_clear_queues(struct rte_eth_dev *dev) if (rxq != NULL) { igb_rx_queue_release_mbufs(rxq); igb_reset_rx_queue(rxq); + dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; } } } @@ -2442,6 +2444,7 @@ eth_igb_rx_init(struct rte_eth_dev *dev) rxdctl |= ((rxq->hthresh & 0x1F) << 8); rxdctl |= ((rxq->wthresh & 0x1F) << 16); E1000_WRITE_REG(hw, E1000_RXDCTL(rxq->reg_idx), rxdctl); + dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; } if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_SCATTER) { @@ -2606,6 +2609,7 @@ eth_igb_tx_init(struct rte_eth_dev *dev) txdctl |= ((txq->wthresh & 0x1F) << 16); txdctl |= E1000_TXDCTL_QUEUE_ENABLE; E1000_WRITE_REG(hw, E1000_TXDCTL(txq->reg_idx), txdctl); + dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; } /* Program the Transmit Control Register. */