From patchwork Tue Aug 8 08:49:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankur Dwivedi X-Patchwork-Id: 129940 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3030C43007; Tue, 8 Aug 2023 10:50:29 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1E02D4325A; Tue, 8 Aug 2023 10:50:29 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 1097C43247 for ; Tue, 8 Aug 2023 10:50:26 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3781ixWU005801 for ; Tue, 8 Aug 2023 01:50:26 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=w002lnHtB9AEuMCvawVwIsohamwZe4MDDhWDbGYbr7A=; b=E9yoMiQihN6N0dMjIetDbyBfxy5N/q1242cF7EiNprF8MbRzE17iQ9yzkitalgq3CmB+ NvkNJMB32hZRiCt+pIpLVI2FNgRv229x9LGNFChEYNMydSuzqC7At/pewOZJ/qcevsFT v71Opvp6K1YWFf9Oj0kH06xS5Mq9V1a9bj0k6TN03OIrfFMv8NISE8w5nlMWAX7at2fE Jm8HwlfftN10wnn3EtjABnHnty44IZ8aV5H1oBkvhk+i5OyRsvY5NZ7jV406YVk40bsW vAOVKACctn7QKIkSTzRp6IpkhAAY6V+imc6ZReCYf/Z+vVLace+gUF7rh7bfmFyC1Ck4 XQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3sb6wwaapk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 08 Aug 2023 01:50:26 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 8 Aug 2023 01:50:24 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 8 Aug 2023 01:50:24 -0700 Received: from localhost.localdomain (unknown [10.28.36.185]) by maili.marvell.com (Postfix) with ESMTP id 156323F704E; Tue, 8 Aug 2023 01:50:21 -0700 (PDT) From: Ankur Dwivedi To: CC: , , , , , Ankur Dwivedi Subject: [PATCH v2 2/2] net/cnxk: add get flow aged ops Date: Tue, 8 Aug 2023 14:19:52 +0530 Message-ID: <20230808084952.2460758-3-adwivedi@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230808084952.2460758-1-adwivedi@marvell.com> References: <20230727115926.2252988-1-adwivedi@marvell.com> <20230808084952.2460758-1-adwivedi@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: H-pSMgmQ7FpCK5zaPdSStQzjdssPh87v X-Proofpoint-ORIG-GUID: H-pSMgmQ7FpCK5zaPdSStQzjdssPh87v X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-08_07,2023-08-03_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adds get flow aged ops in CNXK driver. Also adds the devargs to get the poll frequency of control thread. Signed-off-by: Ankur Dwivedi --- doc/guides/nics/cnxk.rst | 12 +++++++ doc/guides/nics/features/cnxk.ini | 1 + doc/guides/nics/features/cnxk_vf.ini | 1 + drivers/net/cnxk/cnxk_ethdev_devargs.c | 21 +++++++++++- drivers/net/cnxk/cnxk_flow.c | 45 ++++++++++++++++++++++++++ 5 files changed, 79 insertions(+), 1 deletion(-) diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst index 9229056f6f..dc71ab7fc3 100644 --- a/doc/guides/nics/cnxk.rst +++ b/doc/guides/nics/cnxk.rst @@ -581,6 +581,18 @@ Runtime Config Options for inline device With the above configuration, driver would poll for soft expiry events every 1000 usec. +- ``NPC MCAM Aging poll frequency in seconds`` (default ``10``) + + Poll frequency for aging control thread can be specified by + ``aging_poll_freq`` ``devargs`` parameter. + + For example:: + + -a 0002:01:00.2,aging_poll_freq=50 + + With the above configuration, driver would poll for aging flows every 50 + seconds. + Debugging Options ----------------- diff --git a/doc/guides/nics/features/cnxk.ini b/doc/guides/nics/features/cnxk.ini index 838e781d6d..ebedbd0588 100644 --- a/doc/guides/nics/features/cnxk.ini +++ b/doc/guides/nics/features/cnxk.ini @@ -80,6 +80,7 @@ vxlan = Y vxlan_gpe = Y [rte_flow actions] +age = Y count = Y drop = Y flag = Y diff --git a/doc/guides/nics/features/cnxk_vf.ini b/doc/guides/nics/features/cnxk_vf.ini index 470c45ce59..0e9ad94382 100644 --- a/doc/guides/nics/features/cnxk_vf.ini +++ b/doc/guides/nics/features/cnxk_vf.ini @@ -71,6 +71,7 @@ vxlan = Y vxlan_gpe = Y [rte_flow actions] +age = Y count = Y drop = Y flag = Y diff --git a/drivers/net/cnxk/cnxk_ethdev_devargs.c b/drivers/net/cnxk/cnxk_ethdev_devargs.c index e1a0845ece..8e862be933 100644 --- a/drivers/net/cnxk/cnxk_ethdev_devargs.c +++ b/drivers/net/cnxk/cnxk_ethdev_devargs.c @@ -245,6 +245,19 @@ parse_sdp_channel_mask(const char *key, const char *value, void *extra_args) return 0; } +static int +parse_val_u16(const char *key, const char *value, void *extra_args) +{ + RTE_SET_USED(key); + uint16_t val; + + val = atoi(value); + + *(uint16_t *)extra_args = val; + + return 0; +} + #define CNXK_RSS_RETA_SIZE "reta_size" #define CNXK_SCL_ENABLE "scalar_enable" #define CNXK_TX_COMPL_ENA "tx_compl_ena" @@ -265,10 +278,12 @@ parse_sdp_channel_mask(const char *key, const char *value, void *extra_args) #define CNXK_CUSTOM_SA_ACT "custom_sa_act" #define CNXK_SQB_SLACK "sqb_slack" #define CNXK_NIX_META_BUF_SZ "meta_buf_sz" +#define CNXK_FLOW_AGING_POLL_FREQ "aging_poll_freq" int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev) { + uint16_t aging_thread_poll_freq = ROC_NPC_AGE_POLL_FREQ_MIN; uint16_t reta_sz = ROC_NIX_RSS_RETA_SZ_64; uint16_t sqb_count = CNXK_NIX_TX_MAX_SQB; struct flow_pre_l2_size_info pre_l2_info; @@ -338,6 +353,8 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev) rte_kvargs_process(kvlist, CNXK_SQB_SLACK, &parse_sqb_count, &sqb_slack); rte_kvargs_process(kvlist, CNXK_NIX_META_BUF_SZ, &parse_meta_bufsize, &meta_buf_sz); + rte_kvargs_process(kvlist, CNXK_FLOW_AGING_POLL_FREQ, &parse_val_u16, + &aging_thread_poll_freq); rte_kvargs_free(kvlist); null_devargs: @@ -369,6 +386,7 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev) dev->npc.pre_l2_size_offset = pre_l2_info.pre_l2_size_off; dev->npc.pre_l2_size_offset_mask = pre_l2_info.pre_l2_size_off_mask; dev->npc.pre_l2_size_shift_dir = pre_l2_info.pre_l2_size_shift_dir; + dev->npc.flow_age.aging_poll_freq = aging_thread_poll_freq; return 0; exit: return -EINVAL; @@ -390,4 +408,5 @@ RTE_PMD_REGISTER_PARAM_STRING(net_cnxk, CNXK_NO_INL_DEV "=0" CNXK_SDP_CHANNEL_MASK "=<1-4095>/<1-4095>" CNXK_CUSTOM_SA_ACT "=1" - CNXK_SQB_SLACK "=<12-512>"); + CNXK_SQB_SLACK "=<12-512>" + CNXK_FLOW_AGING_POLL_FREQ "=<10-65535>"); diff --git a/drivers/net/cnxk/cnxk_flow.c b/drivers/net/cnxk/cnxk_flow.c index 3b8348ae9c..e0aeb5ea5f 100644 --- a/drivers/net/cnxk/cnxk_flow.c +++ b/drivers/net/cnxk/cnxk_flow.c @@ -230,6 +230,10 @@ cnxk_map_actions(struct rte_eth_dev *eth_dev, const struct rte_flow_attr *attr, in_actions[i].type = ROC_NPC_ACTION_TYPE_METER; in_actions[i].conf = actions->conf; break; + case RTE_FLOW_ACTION_TYPE_AGE: + in_actions[i].type = ROC_NPC_ACTION_TYPE_AGE; + in_actions[i].conf = actions->conf; + break; default: plt_npc_dbg("Action is not supported = %d", actions->type); @@ -480,10 +484,51 @@ cnxk_flow_dev_dump(struct rte_eth_dev *eth_dev, struct rte_flow *flow, return 0; } +static int +cnxk_flow_get_aged_flows(struct rte_eth_dev *eth_dev, void **context, + uint32_t nb_contexts, struct rte_flow_error *err) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct roc_npc *roc_npc = &dev->npc; + struct roc_npc_flow_age *flow_age; + uint32_t start_id; + uint32_t end_id; + int cnt = 0; + uint32_t sn; + uint32_t i; + + RTE_SET_USED(err); + + flow_age = &roc_npc->flow_age; + + do { + sn = plt_seqcount_read_begin(&flow_age->seq_cnt); + + if (nb_contexts == 0) { + cnt = flow_age->aged_flows_cnt; + } else { + start_id = flow_age->start_id; + end_id = flow_age->end_id; + for (i = start_id; i <= end_id; i++) { + if ((int)nb_contexts == cnt) + break; + if (plt_bitmap_get(flow_age->aged_flows, i)) { + context[cnt] = + roc_npc_aged_flow_ctx_get(roc_npc, i); + cnt++; + } + } + } + } while (plt_seqcount_read_retry(&flow_age->seq_cnt, sn)); + + return cnt; +} + struct rte_flow_ops cnxk_flow_ops = { .validate = cnxk_flow_validate, .flush = cnxk_flow_flush, .query = cnxk_flow_query, .isolate = cnxk_flow_isolate, .dev_dump = cnxk_flow_dev_dump, + .get_aged_flows = cnxk_flow_get_aged_flows, };