From patchwork Wed Aug 9 01:32:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 129998 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 629AB43011; Wed, 9 Aug 2023 03:33:50 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 62CB643261; Wed, 9 Aug 2023 03:33:34 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id EF9C94325E for ; Wed, 9 Aug 2023 03:33:32 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691544813; x=1723080813; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Z3AcEGvgUNJVgaVR3NfSu11+MYBNIqH0FSeYZxjcdpk=; b=caxucMg5L8qZjs3IKIfjF21Xp0YZqpGeoleq8W3uFADMlyBD4TN3zOLg m0IY/f5uTuVhDPSMBSQOdeqiTqN64yxJZoaKEBojv6pqXnh5hQCa35gNu rqErGnIlPQzj/5kEUCkHBRTtxHrdPFb1fqC3uJLXSqxEw5Yt4NlJD2e7i FIJ/fxS+IC9tDNoRNonG//EV89JToscxbINSd7DlaZxdek0vyL8sahNit Myy0/xreBFVgCJHrQluSp06rMJ/lLtzHM/mum2m7V/REsJz5cRbKH3dSV wev9MNeJyhZBqYqOZnYl/g2r86FaAH/qvN+aDCc/ddaHUtMd3LX19IbXx w==; X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="374704471" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="374704471" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2023 18:33:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="845735070" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="845735070" Received: from dpdk-wenjing-02.sh.intel.com ([10.67.119.75]) by fmsmga002.fm.intel.com with ESMTP; 08 Aug 2023 18:33:30 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Madhu Chittim Subject: [PATCH 04/14] common/idpf/base: remove mailbox registers Date: Wed, 9 Aug 2023 01:32:58 +0000 Message-Id: <20230809013308.1449103-5-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230809013308.1449103-1-wenjing.qiao@intel.com> References: <20230809013308.1449103-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Simei Su Removing mailbox register offsets as the mapping to device register offsets are different between CVL and MEV (they are swapped out) individual drivers will define the offsets based on how registers are hardware addressed. However the it will begin with VDEV_MBX_START offset. Signed-off-by: Madhu Chittim Signed-off-by: Simei Su --- .mailmap | 1 + drivers/common/idpf/base/siov_regs.h | 13 ++----------- 2 files changed, 3 insertions(+), 11 deletions(-) diff --git a/.mailmap b/.mailmap index af452d54c6..f23f8fecfa 100644 --- a/.mailmap +++ b/.mailmap @@ -1641,3 +1641,4 @@ Zyta Szpak Jayaprakash Shanmugam Zhenning Xiao Josh Hay +Madhu Chittim diff --git a/drivers/common/idpf/base/siov_regs.h b/drivers/common/idpf/base/siov_regs.h index fad329601a..7e1ae2e300 100644 --- a/drivers/common/idpf/base/siov_regs.h +++ b/drivers/common/idpf/base/siov_regs.h @@ -4,16 +4,6 @@ #ifndef _SIOV_REGS_H_ #define _SIOV_REGS_H_ #define VDEV_MBX_START 0x20000 /* Begin at 128KB */ -#define VDEV_MBX_ATQBAL (VDEV_MBX_START + 0x0000) -#define VDEV_MBX_ATQBAH (VDEV_MBX_START + 0x0004) -#define VDEV_MBX_ATQLEN (VDEV_MBX_START + 0x0008) -#define VDEV_MBX_ATQH (VDEV_MBX_START + 0x000C) -#define VDEV_MBX_ATQT (VDEV_MBX_START + 0x0010) -#define VDEV_MBX_ARQBAL (VDEV_MBX_START + 0x0014) -#define VDEV_MBX_ARQBAH (VDEV_MBX_START + 0x0018) -#define VDEV_MBX_ARQLEN (VDEV_MBX_START + 0x001C) -#define VDEV_MBX_ARQH (VDEV_MBX_START + 0x0020) -#define VDEV_MBX_ARQT (VDEV_MBX_START + 0x0024) #define VDEV_GET_RSTAT 0x21000 /* 132KB for RSTAT */ /* Begin at offset after 1MB (after 256 4k pages) */ @@ -43,5 +33,6 @@ #define VDEV_INT_ITR_1(_i) (VDEV_INT_DYN_START + ((_i) * 0x1000) + 0x08) #define VDEV_INT_ITR_2(_i) (VDEV_INT_DYN_START + ((_i) * 0x1000) + 0x0C) -/* Next offset to begin at 42MB (0x2A00000) */ +#define SIOV_REG_BAR_SIZE 0x2A00000 +/* Next offset to begin at 42MB + 4K (0x2A00000 + 0x1000) */ #endif /* _SIOV_REGS_H_ */