From patchwork Fri Aug 11 08:57:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130131 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3162C43032; Fri, 11 Aug 2023 10:59:55 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CEF604324E; Fri, 11 Aug 2023 10:59:03 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id A02DF43293 for ; Fri, 11 Aug 2023 10:59:02 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AMk3fg002130 for ; Fri, 11 Aug 2023 01:59:01 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=AryHH6F24PP4iQQsNyXVHNeb0Rr0/6HNr/XXhSKb41M=; b=VFs+5XP455OdM5pWQAKL3hvDy3KAy7T72xYMIB1eHFZ35X9NS5ZZ7GxVbkrfeDJfPFNs GzwQyByKyeNqFWxdKI/wWRPA6G/NcKwCcioLKeHh3WXl3MnZMzIjPMaZAylcH3SaBT2u +MmppwUiquvm3j27nLn/K8IdhKwPGtNdiqa5dkeBNmYDo7uzDi5aGXo2CcMVedzfG1rH vcCE4j+9lm5058d6xenrvF0Y3geQSUfIu2qeOFOGUzjD+pkrJF6L8NK3c7rKpJ5272iG Snj0lrb9mVLBnxLG3ij39nfe3WBqYyAWK8lVnFO110RfbP50EQKJ4sXCLZhWUJEGJta2 zw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8yp9r9e-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 11 Aug 2023 01:59:01 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:59:00 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:59:00 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id E16AD3F706B; Fri, 11 Aug 2023 01:58:57 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 17/31] common/cnxk: expose different params for bp config Date: Fri, 11 Aug 2023 14:27:51 +0530 Message-ID: <20230811085805.441256-17-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: CkpUZa0i8-jbgdD4bP89YUwuyhzYVZ2D X-Proofpoint-GUID: CkpUZa0i8-jbgdD4bP89YUwuyhzYVZ2D X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sunil Kumar Kori Currently same bp percentage is applied on SPB and LPB pool but both pools can be configured with different bp level. Added one more parameter so that separate threshold parameters can be passed for SPB and LPB pools. Signed-off-by: Sunil Kumar Kori --- drivers/common/cnxk/roc_nix.h | 3 ++- drivers/common/cnxk/roc_nix_fc.c | 14 +++++++++----- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 377b9604ea..bb55fbe971 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -196,10 +196,11 @@ struct roc_nix_fc_cfg { uint32_t rq; uint16_t tc; uint16_t cq_drop; - bool enable; uint64_t pool; uint64_t spb_pool; uint64_t pool_drop_pct; + uint64_t spb_pool_drop_pct; + bool enable; } rq_cfg; struct { diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c index 2a58567751..12bfb9816b 100644 --- a/drivers/common/cnxk/roc_nix_fc.c +++ b/drivers/common/cnxk/roc_nix_fc.c @@ -282,8 +282,8 @@ static int nix_fc_rq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg) { struct nix *nix = roc_nix_to_nix_priv(roc_nix); + uint64_t pool_drop_pct, spb_pool_drop_pct; struct roc_nix_fc_cfg tmp; - uint64_t pool_drop_pct; struct roc_nix_rq *rq; int rc; @@ -295,14 +295,18 @@ nix_fc_rq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg) if (fc_cfg->rq_cfg.enable && !pool_drop_pct) pool_drop_pct = ROC_NIX_AURA_THRESH; - roc_nix_fc_npa_bp_cfg(roc_nix, fc_cfg->rq_cfg.pool, - fc_cfg->rq_cfg.enable, roc_nix->force_rx_aura_bp, - fc_cfg->rq_cfg.tc, pool_drop_pct); + roc_nix_fc_npa_bp_cfg(roc_nix, fc_cfg->rq_cfg.pool, fc_cfg->rq_cfg.enable, + roc_nix->force_rx_aura_bp, fc_cfg->rq_cfg.tc, pool_drop_pct); if (rq->spb_ena) { + spb_pool_drop_pct = fc_cfg->rq_cfg.spb_pool_drop_pct; + /* Use default value for zero pct */ + if (!spb_pool_drop_pct) + spb_pool_drop_pct = ROC_NIX_AURA_THRESH; + roc_nix_fc_npa_bp_cfg(roc_nix, fc_cfg->rq_cfg.spb_pool, fc_cfg->rq_cfg.enable, roc_nix->force_rx_aura_bp, - fc_cfg->rq_cfg.tc, pool_drop_pct); + fc_cfg->rq_cfg.tc, spb_pool_drop_pct); } if (roc_nix->local_meta_aura_ena && roc_nix->meta_aura_handle)