From patchwork Fri Aug 11 08:57:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130116 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D690F43032; Fri, 11 Aug 2023 10:58:19 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6370A43254; Fri, 11 Aug 2023 10:58:18 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 77A234325B for ; Fri, 11 Aug 2023 10:58:16 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AMjlID001539 for ; Fri, 11 Aug 2023 01:58:15 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=vJ+BPju+IfNBe5MDSFIrN0RQvc9MiW/rigEMw5zTwy4=; b=A6pX4aDNXeUkQtbr6FiEGK2Df7RP+MVvsdyAyrQss0rIgA8RBx8O4yVLczUWIzfmapzX YBVmKGHMnuvXkP1qbNRYuiv52vi2tjZKS/FPXrlRK38NVlcfgxdl/7A6P77vnSX3vVio tbLsQMUMLCW1OLDn4hYAkXEjgcLaw2UAE/LFtooHx0gayDGZsq7mLGw2hMVufDAw/yjs 6XOFXhvtjOMg3PA7PYPdWRGmtM14BfNWRdhgyirfUaQZCSWQEHir7sjf2Hfz9pUromdB QWTZn/jYVFdtFmOZGfqKsYVf6gFE44nXjELp5teNnd7crF1w9AZF11fDjvFOhq1vCH5v /A== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8yp9r5c-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 11 Aug 2023 01:58:15 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:58:13 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:58:13 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 611743F706A; Fri, 11 Aug 2023 01:58:11 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Rakesh Kudurumalla Subject: [PATCH 02/31] common/cnxk: optimize time while configuring fc on VF Date: Fri, 11 Aug 2023 14:27:36 +0530 Message-ID: <20230811085805.441256-2-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: vQRtR5gweMJ0OOscrqC0rPXSgyfCs6Z5 X-Proofpoint-GUID: vQRtR5gweMJ0OOscrqC0rPXSgyfCs6Z5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Rakesh Kudurumalla PFC configuration function is taking 8 ms due to mailbox communication to check whether sso is connected to RQ and whether back pressure is enabled on each aura. To optimize this time we are updating aura attributes in nixlf and sso_ena parameter in RQ during write configuration and the same updated value is accessed while configuring flow control, reducing time to 6 ms. Signed-off-by: Rakesh Kudurumalla --- drivers/common/cnxk/roc_nix_fc.c | 47 ++++++++---------------------- drivers/common/cnxk/roc_npa.c | 16 +++++++++- drivers/common/cnxk/roc_npa_priv.h | 6 ++++ 3 files changed, 33 insertions(+), 36 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c index 1f5ef960da..d58b35268e 100644 --- a/drivers/common/cnxk/roc_nix_fc.c +++ b/drivers/common/cnxk/roc_nix_fc.c @@ -285,15 +285,11 @@ nix_fc_rq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg) struct roc_nix_fc_cfg tmp; uint64_t pool_drop_pct; struct roc_nix_rq *rq; - int sso_ena = 0, rc; + int rc; rq = nix->rqs[fc_cfg->rq_cfg.rq]; - /* Check whether RQ is connected to SSO or not */ - sso_ena = roc_nix_rq_is_sso_enable(roc_nix, fc_cfg->rq_cfg.rq); - if (sso_ena < 0) - return -EINVAL; - if (sso_ena) { + if (rq->sso_ena) { pool_drop_pct = fc_cfg->rq_cfg.pool_drop_pct; /* Use default value for zero pct */ if (fc_cfg->rq_cfg.enable && !pool_drop_pct) @@ -486,12 +482,10 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui uint32_t aura_id = roc_npa_aura_handle_to_aura(pool_id); struct nix *nix = roc_nix_to_nix_priv(roc_nix); struct npa_lf *lf = idev_npa_obj_get(); - struct npa_aq_enq_req *req; - struct npa_aq_enq_rsp *rsp; + struct npa_aura_attr *aura_attr; uint8_t bp_thresh, bp_intf; - struct mbox *mbox; uint16_t bpid; - int rc, i; + int i; if (roc_nix_is_sdp(roc_nix)) return; @@ -499,30 +493,14 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui if (!lf) return; - mbox = lf->mbox; - req = mbox_alloc_msg_npa_aq_enq(mbox_get(mbox)); - if (req == NULL) { - mbox_put(mbox); - return; - } - - req->aura_id = aura_id; - req->ctype = NPA_AQ_CTYPE_AURA; - req->op = NPA_AQ_INSTOP_READ; - - rc = mbox_process_msg(mbox, (void *)&rsp); - mbox_put(mbox); - if (rc) { - plt_nix_dbg("Failed to read context of aura 0x%" PRIx64, pool_id); - return; - } + aura_attr = &lf->aura_attr[aura_id]; bp_intf = 1 << nix->is_nix1; - bp_thresh = NIX_RQ_AURA_THRESH(drop_percent, rsp->aura.limit >> rsp->aura.shift); + bp_thresh = NIX_RQ_AURA_THRESH(drop_percent, aura_attr->limit >> aura_attr->shift); - bpid = (rsp->aura.bp_ena & 0x1) ? rsp->aura.nix0_bpid : rsp->aura.nix1_bpid; + bpid = (aura_attr->bp_ena & 0x1) ? aura_attr->nix0_bpid : aura_attr->nix1_bpid; /* BP is already enabled. */ - if (rsp->aura.bp_ena && ena) { + if (aura_attr->bp_ena && ena) { /* Disable BP if BPIDs don't match and couldn't add new BPID. */ if (bpid != nix->bpid[tc]) { uint16_t bpid_new = NIX_BPID_INVALID; @@ -537,7 +515,7 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui plt_err("Enabling backpressue failed on aura 0x%" PRIx64, pool_id); } else { - lf->aura_attr[aura_id].ref_count++; + aura_attr->ref_count++; plt_info("Ignoring port=%u tc=%u config on shared aura 0x%" PRIx64, roc_nix->port_id, tc, pool_id); } @@ -547,14 +525,14 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui } /* BP was previously enabled but now disabled skip. */ - if (rsp->aura.bp && ena) + if (aura_attr->bp && ena) return; if (ena) { if (roc_npa_aura_bp_configure(pool_id, nix->bpid[tc], bp_intf, bp_thresh, true)) plt_err("Enabling backpressue failed on aura 0x%" PRIx64, pool_id); else - lf->aura_attr[aura_id].ref_count++; + aura_attr->ref_count++; } else { bool found = !!force; @@ -564,8 +542,7 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui found = true; if (!found) return; - else if ((lf->aura_attr[aura_id].ref_count > 0) && - --lf->aura_attr[aura_id].ref_count) + else if ((aura_attr->ref_count > 0) && --(aura_attr->ref_count)) return; if (roc_npa_aura_bp_configure(pool_id, 0, 0, 0, false)) diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c index 3b9a70028b..d5c3a53b9b 100644 --- a/drivers/common/cnxk/roc_npa.c +++ b/drivers/common/cnxk/roc_npa.c @@ -535,6 +535,8 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size, if (rc) goto stack_mem_free; + lf->aura_attr[aura_id].shift = aura->shift; + lf->aura_attr[aura_id].limit = aura->limit; *aura_handle = roc_npa_aura_handle_gen(aura_id, lf->base); /* Update aura count */ roc_npa_aura_op_cnt_set(*aura_handle, 0, block_count); @@ -657,6 +659,8 @@ npa_aura_alloc(struct npa_lf *lf, const uint32_t block_count, int pool_id, if (rc) return rc; + lf->aura_attr[aura_id].shift = aura->shift; + lf->aura_attr[aura_id].limit = aura->limit; *aura_handle = roc_npa_aura_handle_gen(aura_id, lf->base); return 0; @@ -735,6 +739,9 @@ roc_npa_aura_limit_modify(uint64_t aura_handle, uint16_t aura_limit) aura_req->aura.limit = aura_limit; aura_req->aura_mask.limit = ~(aura_req->aura_mask.limit); rc = mbox_process(mbox); + if (rc) + goto exit; + lf->aura_attr[aura_req->aura_id].limit = aura_req->aura.limit; exit: mbox_put(mbox); return rc; @@ -931,7 +938,14 @@ roc_npa_aura_bp_configure(uint64_t aura_handle, uint16_t bpid, uint8_t bp_intf, req->aura.bp_ena = bp_intf; req->aura_mask.bp_ena = ~(req->aura_mask.bp_ena); - mbox_process(mbox); + rc = mbox_process(mbox); + if (rc) + goto fail; + + lf->aura_attr[aura_id].nix0_bpid = req->aura.nix0_bpid; + lf->aura_attr[aura_id].nix1_bpid = req->aura.nix1_bpid; + lf->aura_attr[aura_id].bp_ena = req->aura.bp_ena; + lf->aura_attr[aura_id].bp = req->aura.bp; fail: mbox_put(mbox); return rc; diff --git a/drivers/common/cnxk/roc_npa_priv.h b/drivers/common/cnxk/roc_npa_priv.h index 704d93d5dc..060df9ab04 100644 --- a/drivers/common/cnxk/roc_npa_priv.h +++ b/drivers/common/cnxk/roc_npa_priv.h @@ -50,6 +50,12 @@ struct npa_aura_lim { struct npa_aura_attr { int buf_type[ROC_NPA_BUF_TYPE_END]; uint16_t ref_count; + uint64_t nix0_bpid; + uint64_t nix1_bpid; + uint64_t shift; + uint64_t limit; + uint8_t bp_ena; + uint8_t bp; }; struct dev;