From patchwork Fri Aug 11 08:57:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130135 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3EEE043032; Fri, 11 Aug 2023 11:00:17 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5575A43298; Fri, 11 Aug 2023 10:59:16 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 4739F43277 for ; Fri, 11 Aug 2023 10:59:15 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AMk3fm002130 for ; Fri, 11 Aug 2023 01:59:14 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=V3+RY5wc0CjmLx/FR7s0ub+GdjW250n5Z6dH6u36CKs=; b=JZL38n+Oad0ywVbALzYWrnceHNU195EtqD0Z6kcqIqBwO2i3vylAkl5SWug5Ksktsn0r lA7BQmrOTRurug+RfS4n8r5UZ7yQaVIaKPdv8KOspISZwGXq0z07BiVlYqGBamf6x9G6 +GOn/GDVQTXh0267HT5xFEJQjy9S//U+cKJShRFrApVQ8Am4TwCt1eolNCA1ji6hXeig CUl79QvEdCEe6YfQymKTazSWp6KAGjp+06ujiW/ISH2Ne+NL4WBVLRqqN6eczw6p1upk 6hd7T2UIkDSQYjrzG+7s5C4PNhNVgEDjfQ4kX9zM8MHQVZ6KphxI+EyAN2W1aLtib6w+ gw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8yp9raj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 11 Aug 2023 01:59:14 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:59:12 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:59:12 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 720443F706B; Fri, 11 Aug 2023 01:59:10 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 21/31] net/cnxk: fix issue with GCC 4.8 Date: Fri, 11 Aug 2023 14:27:55 +0530 Message-ID: <20230811085805.441256-21-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: FGYt142jMiW7hLl4tHnlvfyhxSSGEG_o X-Proofpoint-GUID: FGYt142jMiW7hLl4tHnlvfyhxSSGEG_o X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fix issue with GCC 4.8 cross compilation of ARM64 for flexible vector conversions. Fixes: ec28231ed260 ("net/cnxk: support reassembly of multi-segment packets") Signed-off-by: Nithin Dabilpuram --- drivers/net/cnxk/cn10k_rx.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h index 8148866e44..0dc0b0595c 100644 --- a/drivers/net/cnxk/cn10k_rx.h +++ b/drivers/net/cnxk/cn10k_rx.h @@ -164,9 +164,9 @@ nix_sec_reass_frags_get(const struct cpt_parse_hdr_s *hdr, struct rte_mbuf **nex next_mbufs[1] = ((struct rte_mbuf *)vgetq_lane_u64(frags23, 0) - 1); next_mbufs[2] = ((struct rte_mbuf *)vgetq_lane_u64(frags23, 1) - 1); - fsz_w1 = vdup_n_u64(finfo->w1.u64); + fsz_w1 = vreinterpret_u16_u64(vdup_n_u64(finfo->w1.u64)); fsz_w1 = vrev16_u8(fsz_w1); - return vget_lane_u64(fsz_w1, 0); + return vget_lane_u64(vreinterpret_u64_u16(fsz_w1), 0); } static __rte_always_inline void @@ -174,7 +174,7 @@ nix_sec_reass_first_frag_update(struct rte_mbuf *head, const uint8_t *m_ipptr, uint64_t fsz, uint64_t cq_w1, uint16_t *ihl) { union nix_rx_parse_u *rx = (union nix_rx_parse_u *)((uintptr_t)(head + 1) + 8); - uint16_t fragx_sum = vaddv_u16(vdup_n_u64(fsz)); + uint16_t fragx_sum = vaddv_u16(vreinterpret_u16_u64(vdup_n_u64(fsz))); uint8_t lcptr = rx->lcptr; uint16_t tot_len; uint32_t cksum;