From patchwork Fri Aug 11 08:57:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130117 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 86AF043032; Fri, 11 Aug 2023 10:58:26 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 754D143261; Fri, 11 Aug 2023 10:58:22 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id E4DB240F16 for ; Fri, 11 Aug 2023 10:58:20 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AN2WUt011282 for ; Fri, 11 Aug 2023 01:58:20 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=QtR+mqZw/a1P8k+TMIfR+tFsNhAXsr2/SfyTjqJNJco=; b=FWN0DYj6PtVNrPj4Lf7+C7UBnR1kx3P/1T374/46Me0u2YXTPhSDTyMG/OQZcQiRzCxY 1vGwlZ+HvQdnxnL8BuLvf3/U+s83dsB3gzFfvzGkJWQbd2QG+Hobvu+T4W9/j0HCY7r0 0LjZXjcRdWKdtCV1s28H097g+IQlQZ5SMzUGRH3dDBgMi3/CnQKe7xHF11ek1Bis7soE jb9etKPjkAq0gFMNtyMEqY6QaqloQuZ7S4uu/edcCQFIQGOM8ECoYsm+ujz1sph82ccP hDkE9iHPSm8BKxfnwnh6IWFm/9yitSpEE+8ASten4WXdRNYJ0tHsyJaUM6m2T873c0Ul KQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8ya1g7p-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 11 Aug 2023 01:58:20 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:58:18 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:58:18 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 8B1643F706C; Fri, 11 Aug 2023 01:58:14 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 03/31] common/cnxk: use only user sqb slack when provided Date: Fri, 11 Aug 2023 14:27:37 +0530 Message-ID: <20230811085805.441256-3-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: CwB7soMdEOIdEhY66KFXRZRi4ECGVBR_ X-Proofpoint-GUID: CwB7soMdEOIdEhY66KFXRZRi4ECGVBR_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Satha Rao This patch preferred user provided argument while configuring slack. If no platform argument given then by default MAX(24, 30% of SQ size) was configured as slack. Currently even if user provided SQB slack, we take max of internally calculated value and user given one Signed-off-by: Satha Rao --- drivers/common/cnxk/roc_nix_queue.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index 08e8bf7ea2..5e689d08be 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -7,6 +7,9 @@ #include "roc_api.h" #include "roc_priv.h" +/* Default SQB slack per SQ */ +#define ROC_NIX_SQB_SLACK_DFLT 24 + static inline uint32_t nix_qsize_to_val(enum nix_q_size qsize) { @@ -1012,7 +1015,10 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq) sq->sqes_per_sqb_log2 = (uint16_t)plt_log2_u32(sqes_per_sqb); sq->nb_sqb_bufs_adj = nb_sqb_bufs; - nb_sqb_bufs += PLT_MAX(thr, roc_nix->sqb_slack); + if (roc_nix->sqb_slack) + nb_sqb_bufs += roc_nix->sqb_slack; + else + nb_sqb_bufs += PLT_MAX((int)thr, (int)ROC_NIX_SQB_SLACK_DFLT); /* Explicitly set nat_align alone as by default pool is with both * nat_align and buf_offset = 1 which we don't want for SQB. */