From patchwork Fri Aug 11 08:57:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130118 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8AECB43032; Fri, 11 Aug 2023 10:58:32 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 817AA43266; Fri, 11 Aug 2023 10:58:23 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 6A4D740F16 for ; Fri, 11 Aug 2023 10:58:22 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AMjlLm001536 for ; Fri, 11 Aug 2023 01:58:21 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=mbao0JEJAn2WMgMgLFxmyByE8ETbY4eQO+ERdUaNnMY=; b=KycYRiiE4cZw/irlOxbxcI67HeF5gxb1dGfcq47sUYes9DaQpOVW86w7K6zUJ499ttAp ID/+3e0y8gVXNPKqbf91ii7jDASPJW9IY1t7SSCPJwepgms/A1tq9YnQY+hVknTMlijZ jwlzfR5PUo8lJzxZgeeUOo1c+tG0EloerkS7cvmiMgL8PXyNDu15Gkqzz+O5MeARvccx jk2cc68uRgA5ez8PWxph3GwZQD1zGvz4IgB3cc1vKYpneWcK7fIFEKLCqpyyFPsc0cJf I5gOW5GmpWTi+Hp41BwlBeU6FSWzWTRY42Ino/3ogj4aNcNYsIr82rH6k5nDh+ZN0m2o TQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8yp9r5w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 11 Aug 2023 01:58:21 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:58:19 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:58:19 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 9848B3F7081; Fri, 11 Aug 2023 01:58:17 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 04/31] common/cnxk: add workaround for CPT ctx fetch issue Date: Fri, 11 Aug 2023 14:27:38 +0530 Message-ID: <20230811085805.441256-4-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: hcobNQOL1bhEBHSc67xOl8kwErKH-LdO X-Proofpoint-GUID: hcobNQOL1bhEBHSc67xOl8kwErKH-LdO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add workaround for CPT context fetch issue in CN10KB by setting CTX_ILEN to that of CTX_SIZE and enabling FLR_FLUSH in CPT_LF_CTX_CTL. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_cpt.c | 23 ++++++++++++++++++++--- drivers/common/cnxk/roc_cpt.h | 2 ++ drivers/common/cnxk/roc_cpt_priv.h | 4 ++-- drivers/common/cnxk/roc_errata.h | 7 +++++++ drivers/common/cnxk/roc_ie_ot.h | 3 +++ drivers/common/cnxk/roc_mbox.h | 4 ++++ drivers/common/cnxk/roc_nix_inl.c | 14 +++++++++++++- drivers/common/cnxk/roc_nix_inl_dev.c | 10 +++++++++- 8 files changed, 60 insertions(+), 7 deletions(-) diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index d235ff51ca..981e85a204 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -331,6 +331,8 @@ roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_inline_ipse req->param2 = cfg->param2; req->opcode = cfg->opcode; req->bpid = cfg->bpid; + req->ctx_ilen_valid = cfg->ctx_ilen_valid; + req->ctx_ilen = cfg->ctx_ilen; rc = mbox_process(mbox); exit: @@ -460,8 +462,8 @@ cpt_available_lfs_get(struct dev *dev, uint16_t *nb_lf) } int -cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blkaddr, - bool inl_dev_sso) +cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blkaddr, bool inl_dev_sso, + bool ctx_ilen_valid, uint8_t ctx_ilen) { struct cpt_lf_alloc_req_msg *req; struct mbox *mbox = mbox_get(dev->mbox); @@ -485,6 +487,8 @@ cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blkaddr, req->sso_pf_func = idev_sso_pffunc_get(); req->eng_grpmsk = eng_grpmsk; req->blkaddr = blkaddr; + req->ctx_ilen_valid = ctx_ilen_valid; + req->ctx_ilen = ctx_ilen; rc = mbox_process(mbox); exit: @@ -587,6 +591,8 @@ roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf) struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt); uint8_t blkaddr[ROC_CPT_MAX_BLKS]; struct msix_offset_rsp *rsp; + bool ctx_ilen_valid = false; + uint16_t ctx_ilen = 0; uint8_t eng_grpmsk; int blknum = 0; int rc, i; @@ -618,7 +624,13 @@ roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf) (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_SE]) | (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_IE]); - rc = cpt_lfs_alloc(&cpt->dev, eng_grpmsk, blkaddr[blknum], false); + if (roc_errata_cpt_has_ctx_fetch_issue()) { + ctx_ilen_valid = true; + /* Inbound SA size is max context size */ + ctx_ilen = (PLT_ALIGN(ROC_OT_IPSEC_SA_SZ_MAX, ROC_ALIGN) / 128) - 1; + } + + rc = cpt_lfs_alloc(&cpt->dev, eng_grpmsk, blkaddr[blknum], false, ctx_ilen_valid, ctx_ilen); if (rc) goto lfs_detach; @@ -1108,6 +1120,11 @@ roc_cpt_iq_enable(struct roc_cpt_lf *lf) lf_inprog.s.eena = 1; plt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG); + if (roc_errata_cpt_has_ctx_fetch_issue()) { + /* Enable flush on FLR */ + plt_write64(1, lf->rbase + CPT_LF_CTX_CTL); + } + cpt_lf_dump(lf); } diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index 910bd37a0c..787bccb27d 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -161,6 +161,8 @@ struct roc_cpt_inline_ipsec_inb_cfg { uint16_t bpid; uint32_t credit_th; uint8_t egrp; + uint8_t ctx_ilen_valid : 1; + uint8_t ctx_ilen : 7; }; int __roc_api roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, diff --git a/drivers/common/cnxk/roc_cpt_priv.h b/drivers/common/cnxk/roc_cpt_priv.h index 61dec9a168..4ed87c857b 100644 --- a/drivers/common/cnxk/roc_cpt_priv.h +++ b/drivers/common/cnxk/roc_cpt_priv.h @@ -21,8 +21,8 @@ roc_cpt_to_cpt_priv(struct roc_cpt *roc_cpt) int cpt_lfs_attach(struct dev *dev, uint8_t blkaddr, bool modify, uint16_t nb_lf); int cpt_lfs_detach(struct dev *dev); -int cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blk, - bool inl_dev_sso); +int cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blk, bool inl_dev_sso, + bool ctx_ilen_valid, uint8_t ctx_ilen); int cpt_lfs_free(struct dev *dev); int cpt_lf_init(struct roc_cpt_lf *lf); void cpt_lf_fini(struct roc_cpt_lf *lf); diff --git a/drivers/common/cnxk/roc_errata.h b/drivers/common/cnxk/roc_errata.h index 22d2406e94..6f84e06603 100644 --- a/drivers/common/cnxk/roc_errata.h +++ b/drivers/common/cnxk/roc_errata.h @@ -82,6 +82,13 @@ roc_errata_cpt_hang_on_x2p_bp(void) return roc_model_is_cn10ka_a0() || roc_model_is_cn10ka_a1(); } +/* Errata IPBUCPT-38756 */ +static inline bool +roc_errata_cpt_has_ctx_fetch_issue(void) +{ + return roc_model_is_cn10kb(); +} + /* IPBUNIXRX-40400 */ static inline bool roc_errata_nix_no_meta_aura(void) diff --git a/drivers/common/cnxk/roc_ie_ot.h b/drivers/common/cnxk/roc_ie_ot.h index b7fcdf9ba7..af2691e0eb 100644 --- a/drivers/common/cnxk/roc_ie_ot.h +++ b/drivers/common/cnxk/roc_ie_ot.h @@ -570,6 +570,9 @@ PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, hmac_opad_ipad) == PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, ctx) == 31 * sizeof(uint64_t)); +#define ROC_OT_IPSEC_SA_SZ_MAX \ + (PLT_MAX(sizeof(struct roc_ot_ipsec_inb_sa), sizeof(struct roc_ot_ipsec_outb_sa))) + void __roc_api roc_ot_ipsec_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa, bool is_inline); void __roc_api roc_ot_ipsec_outb_sa_init(struct roc_ot_ipsec_outb_sa *sa); diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 2f85b2f755..f038d3e02b 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -2002,6 +2002,8 @@ struct cpt_lf_alloc_req_msg { uint16_t __io sso_pf_func; uint16_t __io eng_grpmsk; uint8_t __io blkaddr; + uint8_t __io ctx_ilen_valid : 1; + uint8_t __io ctx_ilen : 7; }; #define CPT_INLINE_INBOUND 0 @@ -2083,6 +2085,8 @@ struct cpt_rx_inline_lf_cfg_msg { uint32_t __io credit_th; uint16_t __io bpid; uint32_t __io reserved; + uint8_t __io ctx_ilen_valid : 1; + uint8_t __io ctx_ilen : 7; }; struct cpt_caps_rsp_msg { diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index 16f858f561..5cb1f11f53 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -851,6 +851,11 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix) nix->cpt_nixbpid = bpids[0]; cfg.bpid = nix->cpt_nixbpid; } + + if (roc_errata_cpt_has_ctx_fetch_issue()) { + cfg.ctx_ilen_valid = true; + cfg.ctx_ilen = (ROC_NIX_INL_OT_IPSEC_INB_HW_SZ / 128) - 1; + } } /* Do onetime Inbound Inline config in CPTPF */ @@ -931,7 +936,9 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix) struct dev *dev = &nix->dev; struct msix_offset_rsp *rsp; struct nix_inl_dev *inl_dev; + bool ctx_ilen_valid = false; size_t sa_sz, ring_sz; + uint8_t ctx_ilen = 0; uint16_t sso_pffunc; uint8_t eng_grpmask; uint64_t blkaddr, i; @@ -967,12 +974,17 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix) return rc; } + if (!roc_model_is_cn9k() && roc_errata_cpt_has_ctx_fetch_issue()) { + ctx_ilen = (ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ / 128) - 1; + ctx_ilen_valid = true; + } + /* Alloc CPT LF */ eng_grpmask = (1ULL << ROC_CPT_DFLT_ENG_GRP_SE | 1ULL << ROC_CPT_DFLT_ENG_GRP_SE_IE | 1ULL << ROC_CPT_DFLT_ENG_GRP_AE); rc = cpt_lfs_alloc(dev, eng_grpmask, blkaddr, - !roc_nix->ipsec_out_sso_pffunc); + !roc_nix->ipsec_out_sso_pffunc, ctx_ilen_valid, ctx_ilen); if (rc) { plt_err("Failed to alloc CPT LF resources, rc=%d", rc); goto lf_detach; diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c index d76158e30d..2863d5da51 100644 --- a/drivers/common/cnxk/roc_nix_inl_dev.c +++ b/drivers/common/cnxk/roc_nix_inl_dev.c @@ -176,7 +176,9 @@ nix_inl_cpt_setup(struct nix_inl_dev *inl_dev, bool inl_dev_sso) { struct roc_cpt_lf *lf = &inl_dev->cpt_lf; struct dev *dev = &inl_dev->dev; + bool ctx_ilen_valid = false; uint8_t eng_grpmask; + uint8_t ctx_ilen = 0; int rc; if (!inl_dev->attach_cptlf) @@ -186,7 +188,13 @@ nix_inl_cpt_setup(struct nix_inl_dev *inl_dev, bool inl_dev_sso) eng_grpmask = (1ULL << ROC_CPT_DFLT_ENG_GRP_SE | 1ULL << ROC_CPT_DFLT_ENG_GRP_SE_IE | 1ULL << ROC_CPT_DFLT_ENG_GRP_AE); - rc = cpt_lfs_alloc(dev, eng_grpmask, RVU_BLOCK_ADDR_CPT0, inl_dev_sso); + if (roc_errata_cpt_has_ctx_fetch_issue()) { + ctx_ilen = (ROC_NIX_INL_OT_IPSEC_INB_HW_SZ / 128) - 1; + ctx_ilen_valid = true; + } + + rc = cpt_lfs_alloc(dev, eng_grpmask, RVU_BLOCK_ADDR_CPT0, inl_dev_sso, ctx_ilen_valid, + ctx_ilen); if (rc) { plt_err("Failed to alloc CPT LF resources, rc=%d", rc); return rc;