From patchwork Fri Aug 11 08:57:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130119 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D318843032; Fri, 11 Aug 2023 10:58:40 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D57564326D; Fri, 11 Aug 2023 10:58:26 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 7989743271 for ; Fri, 11 Aug 2023 10:58:25 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AN2LhS011196 for ; Fri, 11 Aug 2023 01:58:25 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=DFn57ShgH1uxGl1zXOkYWT0M/xzx+zDOalUd4p+L/7Q=; b=SxTrTFJjIjI/CyXB1/hHiDBfSXfwjxNKleDoeUg5r6XSZ31yDkDSz93B++du02qYlOSe tKfnLo07NJ/N7uy26McAVSS/BpYLD4oKpwxJHYG0nwN3q50PX6yUDveQA5b2KzDgDsQI 74s0J6dZ+VDB+O9J/E6eMt4bEWV7uBOAIeoNAh4IWaMfdleEPcrL9fXKQ+hCcfkyUB+0 lBa4fUCW1e0A89uQ4mV9Q1a5O0hBviOTExvxfSB5lFWPsEkJVVqco9EfwFCzPHwQ9Lze NTISZ8nLVVqlEG96kNe0qxiObJnBmKIjy1OFPooRfbMs9N9b81ui9UVJTi/0gDGLNOPz hQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8ya1g7y-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 11 Aug 2023 01:58:24 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:58:22 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:58:22 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 877F63F706A; Fri, 11 Aug 2023 01:58:20 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 05/31] common/cnxk: support rate limit on PFC TM tree Date: Fri, 11 Aug 2023 14:27:39 +0530 Message-ID: <20230811085805.441256-5-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: abXP39VS7Av572sl-KKTR-Y0W6LVEyTt X-Proofpoint-GUID: abXP39VS7Av572sl-KKTR-Y0W6LVEyTt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Satha Rao New SQ rate limit API to support SQ rate limit on PFC tree. In PFC tree each SQ had its one to one mapped TL3, this patch configures shaper rate on TL3. Also configures the TL2 with link rate. Signed-off-by: Satha Rao --- drivers/common/cnxk/roc_nix.h | 9 ++- drivers/common/cnxk/roc_nix_tm_ops.c | 98 ++++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 1 + 3 files changed, 106 insertions(+), 2 deletions(-) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 9c2ba9a685..1d84f4de9d 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -707,8 +707,13 @@ int __roc_api roc_nix_tm_node_stats_get(struct roc_nix *roc_nix, /* * TM ratelimit tree API. */ -int __roc_api roc_nix_tm_rlimit_sq(struct roc_nix *roc_nix, uint16_t qid, - uint64_t rate); +int __roc_api roc_nix_tm_rlimit_sq(struct roc_nix *roc_nix, uint16_t qid, uint64_t rate); + +/* + * TM PFC tree ratelimit API. + */ +int __roc_api roc_nix_tm_pfc_rlimit_sq(struct roc_nix *roc_nix, uint16_t qid, uint64_t rate); + /* * TM hierarchy enable/disable API. */ diff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c index 4e88ad1beb..e1cef7a670 100644 --- a/drivers/common/cnxk/roc_nix_tm_ops.c +++ b/drivers/common/cnxk/roc_nix_tm_ops.c @@ -1032,6 +1032,104 @@ roc_nix_tm_init(struct roc_nix *roc_nix) return rc; } +int +roc_nix_tm_pfc_rlimit_sq(struct roc_nix *roc_nix, uint16_t qid, uint64_t rate) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct nix_tm_shaper_profile profile; + struct mbox *mbox = (&nix->dev)->mbox; + struct nix_tm_node *node, *parent; + struct roc_nix_link_info link_info; + + volatile uint64_t *reg, *regval; + struct nix_txschq_config *req; + uint64_t tl2_rate = 0; + uint16_t flags; + uint8_t k = 0; + int rc; + + if ((nix->tm_tree != ROC_NIX_TM_PFC) || !(nix->tm_flags & NIX_TM_HIERARCHY_ENA)) + return NIX_ERR_TM_INVALID_TREE; + + node = nix_tm_node_search(nix, qid, nix->tm_tree); + + /* check if we found a valid leaf node */ + if (!node || !nix_tm_is_leaf(nix, node->lvl) || !node->parent || + node->parent->hw_id == NIX_TM_HW_ID_INVALID) { + return NIX_ERR_TM_INVALID_NODE; + } + + /* Get the link Speed */ + if (roc_nix_mac_link_info_get(roc_nix, &link_info)) + return -EINVAL; + + if (link_info.status) + tl2_rate = link_info.speed * (uint64_t)1E6; + + /* Configure TL3 of leaf node with requested rate */ + parent = node->parent; /* SMQ/MDQ */ + parent = parent->parent; /* TL4 */ + parent = parent->parent; /* TL3 */ + flags = parent->flags; + + req = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox)); + req->lvl = parent->hw_lvl; + reg = req->reg; + regval = req->regval; + + if (rate == 0) { + k += nix_tm_sw_xoff_prep(parent, true, ®[k], ®val[k]); + flags &= ~NIX_TM_NODE_ENABLED; + goto exit; + } + + if (!(flags & NIX_TM_NODE_ENABLED)) { + k += nix_tm_sw_xoff_prep(parent, false, ®[k], ®val[k]); + flags |= NIX_TM_NODE_ENABLED; + } + + /* Use only PIR for rate limit */ + memset(&profile, 0, sizeof(profile)); + profile.peak.rate = rate; + /* Minimum burst of ~4us Bytes of Tx */ + profile.peak.size = + PLT_MAX((uint64_t)roc_nix_max_pkt_len(roc_nix), (4ul * rate) / ((uint64_t)1E6 * 8)); + if (!nix->tm_rate_min || nix->tm_rate_min > rate) + nix->tm_rate_min = rate; + + k += nix_tm_shaper_reg_prep(parent, &profile, ®[k], ®val[k]); +exit: + req->num_regs = k; + rc = mbox_process(mbox); + mbox_put(mbox); + if (rc) + return rc; + + parent->flags = flags; + + /* If link is up then configure TL2 with link speed */ + if (tl2_rate && (flags & NIX_TM_NODE_ENABLED)) { + k = 0; + parent = parent->parent; + req = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox)); + req->lvl = parent->hw_lvl; + reg = req->reg; + regval = req->regval; + + /* Use only PIR for rate limit */ + memset(&profile, 0, sizeof(profile)); + profile.peak.rate = tl2_rate; + /* Minimum burst of ~4us Bytes of Tx */ + profile.peak.size = PLT_MAX((uint64_t)roc_nix_max_pkt_len(roc_nix), + (4ul * tl2_rate) / ((uint64_t)1E6 * 8)); + k += nix_tm_shaper_reg_prep(parent, &profile, ®[k], ®val[k]); + req->num_regs = k; + rc = mbox_process(mbox); + mbox_put(mbox); + } + return rc; +} + int roc_nix_tm_rlimit_sq(struct roc_nix *roc_nix, uint16_t qid, uint64_t rate) { diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 8c71497df8..1436c90e12 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -379,6 +379,7 @@ INTERNAL { roc_nix_tm_node_suspend_resume; roc_nix_tm_prealloc_res; roc_nix_tm_pfc_prepare_tree; + roc_nix_tm_pfc_rlimit_sq; roc_nix_tm_prepare_rate_limited_tree; roc_nix_tm_rlimit_sq; roc_nix_tm_root_has_sp;