From patchwork Tue Aug 22 10:46:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sivaramakrishnan Venkat X-Patchwork-Id: 130675 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 22943430E2; Wed, 23 Aug 2023 09:46:37 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EB795410F1; Wed, 23 Aug 2023 09:46:36 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id AB2B24021D; Tue, 22 Aug 2023 12:46:18 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692701179; x=1724237179; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=p1T4KtM64lTYurXg+yXDnEkpddn8kOmnKRP7EHOGthk=; b=ChHf7wn/WixMvoBxSGBy9R9dlqzR2lA/b3Ue6NcyU96DPhY2vJdhlDit guNVDOomHHaCikE0EgPz5VI15oEnJBtK/L3JzDYlhMwXyQWFXRP3gZpLu nTFdDo63nYdwhdeJDA1Czk+UeybboHENLDLlH0vHHcm388wMgA1AuSUEk soDlW3t76rWhesc4LakPj83/uQtkqejFNujyzY3JasP3qFmXw44AuoL2Y NKQSg2x/0DYEsLjjQVbgqjR5CeTflvWc3v+ICIkDk/YFASWn33p96UgP0 jG/FSxORqQ6V30MOe6Z6yzUhmyH+geCvOrvX9gn51X29nkYbc/6H6MbLJ Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10809"; a="404847195" X-IronPort-AV: E=Sophos;i="6.01,192,1684825200"; d="scan'208";a="404847195" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2023 03:46:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10809"; a="765699043" X-IronPort-AV: E=Sophos;i="6.01,192,1684825200"; d="scan'208";a="765699043" Received: from silpixa00401012.ir.intel.com ([10.243.23.140]) by orsmga008.jf.intel.com with ESMTP; 22 Aug 2023 03:46:15 -0700 From: Sivaramakrishnan VenkatX To: Kai Ji Cc: dev@dpdk.org, stable@dpdk.org, gakhil@marvell.com, ciara.power@intel.com, Sivaramakrishnan VenkatX Subject: [PATCH v1] drivers/crypto: cipher buffer alignment check Date: Tue, 22 Aug 2023 10:46:10 +0000 Message-Id: <20230822104610.954234-1-venkatx.sivaramakrishnan@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 23 Aug 2023 09:46:36 +0200 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Cipher length alignment checked for 3DES-CBC and AES-CBC to avoid slice hang error in QAT CPM1.8 Signed-off-by: Sivaramakrishnan VenkatX --- drivers/crypto/qat/dev/qat_crypto_pmd_gens.h | 21 ++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h index cab7e214c0..98504d925f 100644 --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h @@ -10,6 +10,13 @@ #include "qat_sym_session.h" #include "qat_sym.h" +#define AES_OR_3DES_MISALIGNED (ctx->qat_mode == ICP_QAT_HW_CIPHER_CBC_MODE && \ + ((((ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES128) || \ + (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES192) || \ + (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES256)) && \ + (cipher_param->cipher_length % ICP_QAT_HW_AES_BLK_SZ)) || \ + ((ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_3DES) && \ + (cipher_param->cipher_length % ICP_QAT_HW_3DES_BLK_SZ)))) #define QAT_SYM_DP_GET_MAX_ENQ(q, c, n) \ RTE_MIN((q->max_inflights - q->enqueued + q->dequeued - c), n) @@ -699,6 +706,20 @@ enqueue_one_chain_job_gen1(struct qat_sym_session *ctx, cipher_param->cipher_offset = ofs.ofs.cipher.head; cipher_param->cipher_length = cipher_len; + /* Input cipher length alignment requirement for 3DES-CBC and AES-CBC. + * For 3DES-CBC cipher algo, ESP Payload size requires 8 Byte aligned. + * For AES-CBC cipher algo, ESP Payload size requires 16 Byte aligned. + * The alignment should be guaranteed by the ESP package padding field + * according to the RFC4303. Under this condition, QAT will pass through + * chain job as NULL cipher and NULL auth operation and report misalignment + * error detected. + */ + if (AES_OR_3DES_MISALIGNED) { + QAT_LOG(ERR, "Input cipher length alignment error detected.\n"); + ctx->qat_cipher_alg = ICP_QAT_HW_CIPHER_ALGO_NULL; + ctx->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL; + cipher_param->cipher_length = 0; + } qat_set_cipher_iv(cipher_param, cipher_iv, ctx->cipher_iv.length, req); auth_param->auth_off = ofs.ofs.auth.head;