From patchwork Tue Aug 22 13:16:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aakash Sasidharan X-Patchwork-Id: 130635 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F0362430D0; Tue, 22 Aug 2023 15:16:57 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AC94C4021D; Tue, 22 Aug 2023 15:16:57 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 3DB4740041 for ; Tue, 22 Aug 2023 15:16:56 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37M8ZaK0015708 for ; Tue, 22 Aug 2023 06:16:55 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=BBzPiJEed+Dpr2he99zmLDJ1U7lbuFlSgZKeW/wiSSc=; b=c6Kcghfd1H2Ls+Ko5llUlkO1TGIvr/jRAVEOn8OaiByR/oWBujI6ITO3iW1kLZYnB6/0 meJiMJ5y/dq1r7JxJFZd5YlLbjbV59L2q3oS9ACWAqjT2dViibbYitQqk7Zrt6L0MXfv pO+xOuSCOwgqsdzW9hq6rt6t2ynMl8tEO1jCiBsiiUS7HK9X9fXoZMVF3B6Cra+n+W2S nPUQhlKjP71P0FnIk2Vz0zwuR2HqQ72jyNPBMhmw2+Id1hEaZWPklUVc+MohYYuY2kAT F5lt2l1x8Y3uWf5wgyoP6CRUgdqY42XjawwLaXc7Q7ydAZI/2qaqolsdD4g6Bt7gtGlw Vg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3smdthatpd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 22 Aug 2023 06:16:54 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 22 Aug 2023 06:16:53 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 22 Aug 2023 06:16:53 -0700 Received: from localhost.localdomain (unknown [10.28.36.177]) by maili.marvell.com (Postfix) with ESMTP id B6D865B6930; Tue, 22 Aug 2023 06:16:50 -0700 (PDT) From: Aakash Sasidharan To: Pavan Nikhilesh , Shijith Thotton , Akhil Goyal CC: , , , Subject: [PATCH 1/3] event/cnxk: fix return values for capability API Date: Tue, 22 Aug 2023 18:46:47 +0530 Message-ID: <20230822131649.3509986-1-asasidharan@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Proofpoint-GUID: 5k2e394MaQUU9IRJiEbg5K6M-mCaEWfR X-Proofpoint-ORIG-GUID: 5k2e394MaQUU9IRJiEbg5K6M-mCaEWfR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-22_13,2023-08-22_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org crypto adapter capability now returns -ENOTSUP instead of -EINVAL when event_cnxk or crypto_cnxk device is not available. This would allow unit test to be skipped when the devices are not available. Fixes: 19f81cb59cb4 ("event/cnxk: add crypto adapter operations") Signed-off-by: Aakash Sasidharan Acked-by: Anoob Joseph --- drivers/event/cnxk/cn10k_eventdev.c | 16 ++++++++-------- drivers/event/cnxk/cn9k_eventdev.c | 16 ++++++++-------- drivers/event/cnxk/cnxk_eventdev.h | 4 ++-- 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index 499a3aace7..c5d4be0474 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -911,8 +911,8 @@ static int cn10k_crypto_adapter_caps_get(const struct rte_eventdev *event_dev, const struct rte_cryptodev *cdev, uint32_t *caps) { - CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k"); - CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k"); + CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k", ENOTSUP); + CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k", ENOTSUP); *caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD | RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA | @@ -929,8 +929,8 @@ cn10k_crypto_adapter_qp_add(const struct rte_eventdev *event_dev, { int ret; - CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k"); - CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k"); + CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k", EINVAL); + CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k", EINVAL); cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev); @@ -944,8 +944,8 @@ static int cn10k_crypto_adapter_qp_del(const struct rte_eventdev *event_dev, const struct rte_cryptodev *cdev, int32_t queue_pair_id) { - CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k"); - CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k"); + CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k", EINVAL); + CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k", EINVAL); return cnxk_crypto_adapter_qp_del(cdev, queue_pair_id); } @@ -963,8 +963,8 @@ cn10k_crypto_adapter_vec_limits(const struct rte_eventdev *event_dev, const struct rte_cryptodev *cdev, struct rte_event_crypto_adapter_vector_limits *limits) { - CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k"); - CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k"); + CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k", EINVAL); + CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k", EINVAL); limits->log2_sz = false; limits->min_sz = 0; diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index 6cce5477f0..f77a9d7085 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -942,11 +942,11 @@ cn9k_sso_tx_adapter_queue_del(uint8_t id, const struct rte_eventdev *event_dev, } static int -cn9k_crypto_adapter_caps_get(const struct rte_eventdev *event_dev, - const struct rte_cryptodev *cdev, uint32_t *caps) +cn9k_crypto_adapter_caps_get(const struct rte_eventdev *event_dev, const struct rte_cryptodev *cdev, + uint32_t *caps) { - CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn9k"); - CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn9k"); + CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn9k", ENOTSUP); + CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn9k", ENOTSUP); *caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD | RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA; @@ -962,8 +962,8 @@ cn9k_crypto_adapter_qp_add(const struct rte_eventdev *event_dev, { int ret; - CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn9k"); - CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn9k"); + CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn9k", EINVAL); + CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn9k", EINVAL); cn9k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev); @@ -977,8 +977,8 @@ static int cn9k_crypto_adapter_qp_del(const struct rte_eventdev *event_dev, const struct rte_cryptodev *cdev, int32_t queue_pair_id) { - CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn9k"); - CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn9k"); + CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn9k", EINVAL); + CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn9k", EINVAL); return cnxk_crypto_adapter_qp_del(cdev, queue_pair_id); } diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index 9d95092669..bd50de87c0 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -48,10 +48,10 @@ (min + val / ((max + cnt - 1) / cnt)) #define CNXK_SSO_FLUSH_RETRY_MAX 0xfff -#define CNXK_VALID_DEV_OR_ERR_RET(dev, drv_name) \ +#define CNXK_VALID_DEV_OR_ERR_RET(dev, drv_name, err_val) \ do { \ if (strncmp(dev->driver->name, drv_name, strlen(drv_name))) \ - return -EINVAL; \ + return -err_val; \ } while (0) typedef void *(*cnxk_sso_init_hws_mem_t)(void *dev, uint8_t port_id);