From patchwork Fri Aug 25 10:13:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simei Su X-Patchwork-Id: 130751 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8DB6D430FF; Fri, 25 Aug 2023 12:14:01 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F1F0E43254; Fri, 25 Aug 2023 12:13:52 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 3C025400D5 for ; Fri, 25 Aug 2023 12:13:45 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692958425; x=1724494425; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0XmT7RZkHF6YwsFjzbuTq42EJOdCqeCmASBS87xT2lk=; b=YjP3emgWqLe7ueqBViBmvwLKH5tF/46JKKIRRJmERYi/XraLXJd3eNix 08D7dQbwkfxEUpI9e4diBO8WbPWr5IDAbgTUZInD0awdE7P9LoLED061v n5SOjb/B3bAzCKhEyDnnFzuNe/yPffpkayVMof6QnXXhroV8LXBAK9IV3 eVAau5tuXi53zNWNU+evxBpBUQidfwfyGWTJunphLGuBPc+aVXZRgq6Gp /JtDGhFh4Of6IL2KKI5gDHXeEKu2JpZ7CZagWxYJNEbexepKk3lzBpSX9 aVkg0CV3+RNSDzspCLQcjXVkMudetgTYFl9+g8tQkEnLwgPW4t0TDc51p w==; X-IronPort-AV: E=McAfee;i="6600,9927,10812"; a="441027926" X-IronPort-AV: E=Sophos;i="6.02,195,1688454000"; d="scan'208";a="441027926" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2023 03:13:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10812"; a="772439483" X-IronPort-AV: E=Sophos;i="6.02,195,1688454000"; d="scan'208";a="772439483" Received: from dpdk-simei-icelake.sh.intel.com ([10.67.110.167]) by orsmga001.jf.intel.com with ESMTP; 25 Aug 2023 03:13:38 -0700 From: Simei Su To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Madhu Chittim Subject: [PATCH v2 04/17] common/idpf/base: remove mailbox registers Date: Fri, 25 Aug 2023 18:13:31 +0800 Message-Id: <20230825101344.1828774-5-simei.su@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230825101344.1828774-1-simei.su@intel.com> References: <20230809013308.1449103-1-wenjing.qiao@intel.com> <20230825101344.1828774-1-simei.su@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Removing mailbox register offsets as the mapping to device register offsets are different between CVL and MEV (they are swapped out) individual drivers will define the offsets based on how registers are hardware addressed. However the it will begin with VDEV_MBX_START offset. Signed-off-by: Madhu Chittim Signed-off-by: Simei Su --- .mailmap | 1 + drivers/common/idpf/base/siov_regs.h | 13 ++----------- 2 files changed, 3 insertions(+), 11 deletions(-) diff --git a/.mailmap b/.mailmap index af452d54c6..f23f8fecfa 100644 --- a/.mailmap +++ b/.mailmap @@ -1641,3 +1641,4 @@ Zyta Szpak Jayaprakash Shanmugam Zhenning Xiao Josh Hay +Madhu Chittim diff --git a/drivers/common/idpf/base/siov_regs.h b/drivers/common/idpf/base/siov_regs.h index fad329601a..7e1ae2e300 100644 --- a/drivers/common/idpf/base/siov_regs.h +++ b/drivers/common/idpf/base/siov_regs.h @@ -4,16 +4,6 @@ #ifndef _SIOV_REGS_H_ #define _SIOV_REGS_H_ #define VDEV_MBX_START 0x20000 /* Begin at 128KB */ -#define VDEV_MBX_ATQBAL (VDEV_MBX_START + 0x0000) -#define VDEV_MBX_ATQBAH (VDEV_MBX_START + 0x0004) -#define VDEV_MBX_ATQLEN (VDEV_MBX_START + 0x0008) -#define VDEV_MBX_ATQH (VDEV_MBX_START + 0x000C) -#define VDEV_MBX_ATQT (VDEV_MBX_START + 0x0010) -#define VDEV_MBX_ARQBAL (VDEV_MBX_START + 0x0014) -#define VDEV_MBX_ARQBAH (VDEV_MBX_START + 0x0018) -#define VDEV_MBX_ARQLEN (VDEV_MBX_START + 0x001C) -#define VDEV_MBX_ARQH (VDEV_MBX_START + 0x0020) -#define VDEV_MBX_ARQT (VDEV_MBX_START + 0x0024) #define VDEV_GET_RSTAT 0x21000 /* 132KB for RSTAT */ /* Begin at offset after 1MB (after 256 4k pages) */ @@ -43,5 +33,6 @@ #define VDEV_INT_ITR_1(_i) (VDEV_INT_DYN_START + ((_i) * 0x1000) + 0x08) #define VDEV_INT_ITR_2(_i) (VDEV_INT_DYN_START + ((_i) * 0x1000) + 0x0C) -/* Next offset to begin at 42MB (0x2A00000) */ +#define SIOV_REG_BAR_SIZE 0x2A00000 +/* Next offset to begin at 42MB + 4K (0x2A00000 + 0x1000) */ #endif /* _SIOV_REGS_H_ */