From patchwork Wed Aug 30 02:14:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Chaoyong He X-Patchwork-Id: 130865 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3FD3C41FC8; Wed, 30 Aug 2023 04:19:12 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A507440DDB; Wed, 30 Aug 2023 04:16:19 +0200 (CEST) Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam02on2105.outbound.protection.outlook.com [40.107.212.105]) by mails.dpdk.org (Postfix) with ESMTP id 91E66406BA for ; Wed, 30 Aug 2023 04:16:17 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=BJOmxF3rvFoWtkddG1r/WR+abU+6DtXvbU/fmL/SlESYJgZiTmhOALU2lvZkNiUJxvAbNOpUHzbzBkwo70BCUKFYkugHTj4fxPDYmiTgfC6tUCZ3gEYu1Ns71OheKCHvh60/yRPHn36sOhL9JXg8cvF5b8xOMlxHKNMZE9yt/lVAVyWb/KaTIkimOPxt9yjrGYd4bvxDeniDff/IyqKiuWU1enMGLZJi1I6n1ZjDRqtxkEDcj+DPE6OBaVN3UeLixLc60u5mDMasJSsc0owlKB+1Bo6MEjOufER60CaDZQyUk/fuOhfgTIMCfDisCEmc30lPe+CmT9C6rs5b/4igdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=kawOvL8cPaguqLBQZOKjuZVEcj5PKFzXMXu0qjrWsWQ=; b=cBo4tEqP9r4p/xG4wcMxJVrWSA8ZhqPqy9HtnwVZt+C4MOmC7SNJnXq9m4p0xKNBCAX3XR8JPfwcL8fvYhyhCmeKnzeafOMVmipDT2Q5aitwnmtsWMUaAOlED3G9hwHLl02Fg+1dhnz6sUS98hG4iyZKOVTCftOtYNSgIJlKOetxNCj5TRoaV3sTFsl2kVu+EMTTlMhbz9lYamp+gyX0A+jAttOFNDcrGX3nW2JLqkXJvxX/Ousr8MNzN8NsdU1AwJQM9ZRK5FuuCFspYYUXgUvKO8EdDKCcIg69U1zvslWHpjlBorwdmPwlYZJd8sUXglvymj96oVJ7NFIe7YdRUw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=corigine.com; dmarc=pass action=none header.from=corigine.com; dkim=pass header.d=corigine.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=corigine.onmicrosoft.com; s=selector2-corigine-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=kawOvL8cPaguqLBQZOKjuZVEcj5PKFzXMXu0qjrWsWQ=; b=a2HjCHSWQOSR/gWy35ptwL6ZgFA/tpJb3n+eqP0AXPRwuncXrcQLHfOzjUoUMUbKyAOYxfV3FMIc0uSqgwjYwDaOE2QbtKpVWnQ3m05kTBpu0k09wJvhYZOHZ2i84syXQshpRx1x83I5XY3NcYWZO0vGQC2RwlMRM0RUVehcD7w= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=corigine.com; Received: from SJ0PR13MB5545.namprd13.prod.outlook.com (2603:10b6:a03:424::5) by DM6PR13MB3786.namprd13.prod.outlook.com (2603:10b6:5:229::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6745.18; Wed, 30 Aug 2023 02:16:15 +0000 Received: from SJ0PR13MB5545.namprd13.prod.outlook.com ([fe80::c0f3:c2cc:b5bb:4192]) by SJ0PR13MB5545.namprd13.prod.outlook.com ([fe80::c0f3:c2cc:b5bb:4192%4]) with mapi id 15.20.6699.034; Wed, 30 Aug 2023 02:16:15 +0000 From: Chaoyong He To: dev@dpdk.org Cc: oss-drivers@corigine.com, niklas.soderlund@corigine.com, Chaoyong He Subject: [PATCH v2 27/27] net/nfp: extend the usage of nfp BAR from 8 to 24 Date: Wed, 30 Aug 2023 10:14:57 +0800 Message-Id: <20230830021457.2064750-28-chaoyong.he@corigine.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230830021457.2064750-1-chaoyong.he@corigine.com> References: <20230824110956.1943559-1-chaoyong.he@corigine.com> <20230830021457.2064750-1-chaoyong.he@corigine.com> X-ClientProxiedBy: PH0PR07CA0113.namprd07.prod.outlook.com (2603:10b6:510:4::28) To SJ0PR13MB5545.namprd13.prod.outlook.com (2603:10b6:a03:424::5) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ0PR13MB5545:EE_|DM6PR13MB3786:EE_ X-MS-Office365-Filtering-Correlation-Id: 27d6c717-3a0b-44bf-47fe-08dba8ff16ab X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: SnhXltcY52ZMIWBrHzVIVOZjlwKjwNritd9ua6RXriFqcnbzrTmh4WIDLu2kTWacpZdkXuqqrUhjOW/y4g8jIA60j/aECcnitbGlVouOQljB5ajl4IWLbsUojk1ezIGz00n+OlYv77UDqoDluxZafx+2jzqT28Rdfb40HiTkqxcn401iP2/jvWCCLC6gPPb8MQtoLhtkZ65N+er/0O2CaayIu1P9xhlVJ2z4K9n9ZB5j6Ln8paF3q7L8FixPmKUpnX7+1+vIGkGOKUKfTDuUwV6LkR02s+J3V6pNTD+BPyhaFre12QK+vetc/RVL93YLIpT/X41gSPSwqDJgpQy2lQc4lVyN/lc3iLdfYVv8h08N08zvS40JAYKgg/Pl/TgyALpoq16sve/F+06kt7MlzRvm2C/KDshzdVosXFFlj07fKfhKa701YEQ1wpwFs7OAAXzqcmfA3K6s9FAHjbWvNBPRkCD0QG3a1nfH/2gTb5aBYfAaZkjJjjfX8ArQvj/4N4thhoFIURUPK1CR9GJ75TWSX1M53h61eqSzH0A+6ZvxCXbLjkiOgudNsmg5CaaV21ixlz7TxNJOBcQ7tQAhcX/uErP3/gOeYaeqcWSDFU3bcrBGZ6oylOP8sZBQ0p68uYrl5RGdk/egoiYtMg+JxYzf7wkF8q/RGXb3NUF2P0w= X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:SJ0PR13MB5545.namprd13.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(136003)(366004)(376002)(346002)(396003)(39830400003)(451199024)(186009)(1800799009)(6512007)(6916009)(316002)(38100700002)(41300700001)(38350700002)(2906002)(4326008)(66574015)(30864003)(83380400001)(2616005)(86362001)(44832011)(26005)(36756003)(1076003)(8676002)(5660300002)(107886003)(8936002)(6666004)(6506007)(6486002)(66556008)(66946007)(66476007)(52116002)(478600001); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?6Pb+J2QMGPmYPCZjEHiTywwJMu2o?= =?utf-8?q?TeBHgF7aYZU7j66naQd4cgC2H0ziEMKbwWsEdLp58grbRqZH4mcQqzyIsFlVkSDAU?= =?utf-8?q?e0YTQgH+CpuQZMctEYYvN5/fsYDiXQ0S2fAT3fF31MT9Lo2JlgU1segfUhsWNf57R?= =?utf-8?q?4Y8SFO9XogP2nwMjbFEIX+meKuccp8whKYKfcH51ca1xpGbZgfN19CU6WspjbFIv4?= =?utf-8?q?jW2rqhyB2C8UyxcljWSpxO2WTZbJdz0njBU8DgdrdHAa8SbLtgBbGJaFOlNKz9oRJ?= =?utf-8?q?OsO9s3zVo+nLErWe8u78LYV7qqJlElCRE+YkS+GCU3aBH7ndpxdDEdb2zI7qroLHj?= =?utf-8?q?A6DFDl2Srxd3QsW1do7k5C2NZXwy8dgKTXm3ViXj1hl2xZvDMzF+4eDkJHs8CRLHr?= =?utf-8?q?eV6jB4JMs/TEwomPqVTyG2seNpP/MtZV7xh1bTEqjAeyiG38IAkSe1MSDmYOQbo3o?= =?utf-8?q?VAnAzvsUTM3mjxbZQDi0+U+43H65xVzrCq9IfovznQBKXyK+WeJr5e6CE551dIJqC?= =?utf-8?q?oMtDNtTEimFUOEre3km/qqt2HjtEtuEo50QJkQxWCuI/LPZNsRyOjdF4z5ouh1i47?= =?utf-8?q?5Y0LJI/z8JaUMyYG1oAxBAdoNKV29w/MdCet3uVY3AdTHv6UE7+zeMz8sKq2cExPQ?= =?utf-8?q?UW+/nXwA6hRkRpACvfnfm1vE7oDksp8M0WpTjDT3d6c6nIt9DCC65RWlP9TjRsMoJ?= =?utf-8?q?qy1LPk4mJ2LVEd1pTYNGkNNYQdLQF4veA0DCp+ojwKPwV+JGkGMLjQrFDGefBI14J?= =?utf-8?q?fZt+SDImP3atbNXPmv+JuxutNG4MdDPpvLvAclo3RyJpbLv0sCztg8f9Vvw1oUZyL?= =?utf-8?q?hzAZm5grXt1iM9z+sp0NUQOsd0+PzQZB45aZM8Q1oJQvA/Fm+KDPkM7059vLIJjfX?= =?utf-8?q?+k6ZxTmGHA1B/VgQNkZ3oESfLhNNpOl5xepn6rScAcA5kD+RKAu/sYgE/votGx+bi?= =?utf-8?q?3wJUuSE0lFucg9Um1B27ChrQKy/LtRlHlevFdiYfU3LqBKb7L4XDEO1uhBVRHhKvh?= =?utf-8?q?lnME795U6YTGqjLyC5DW/oKqREHtkAINa6f88nazS9CqqglPPA9Yi7KS+IjkJ++Rz?= =?utf-8?q?nuD9LU6qWmYZ1WW5SvHbutPNEJeSIspgtsXizlyZJtkGKITkrdo8SJDYKU7zhHDU4?= =?utf-8?q?89ROGhFoQKxbtCjsGRbyWhk7itfnNIzJIaUHhK1vBXjyGXGjG/iIbQ5M8gSaUPicO?= =?utf-8?q?uiTm2YKT4hQK7zq9H0Exd+mgh+pNieaNpAuL/3Oq8s9IMus17CCyVl+gjQMlC4ewp?= =?utf-8?q?URd2b6ZP5WKeAhYxuTcCt/AUI3r44WwMRPlGle/OvykJbUaU+ckVYgtCaL9eDvPyo?= =?utf-8?q?kSeQQi6GHgCr3E87A3GaWdNE3Cao9FkGcPQG9Yprddtvyz0PyNpRvc/VfXvbziFgq?= =?utf-8?q?gP0PZv1BvFDWF9HfS3cKHmk5XEGdI+xS+k47fnx/Qp57vEGxcUsC3FD1i7Af46bLe?= =?utf-8?q?N0a01DS9wksMDaWOqvXTmTL81hFN6W/cgkeazeW7qBCWc+cyQ1Q2fEKin4Ji2zQrK?= =?utf-8?q?We0Od9SSexUrr99vaQxgiv9T1UrxNOu21Q=3D=3D?= X-OriginatorOrg: corigine.com X-MS-Exchange-CrossTenant-Network-Message-Id: 27d6c717-3a0b-44bf-47fe-08dba8ff16ab X-MS-Exchange-CrossTenant-AuthSource: SJ0PR13MB5545.namprd13.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Aug 2023 02:16:15.6861 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: fe128f2c-073b-4c20-818e-7246a585940c X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Na5mLKsJmiVPp3OOcbAsxzMdXFO1S3ZH/uJARegeq7Px9tAzs6rGTNcLUT4INO9QSZez1yvdIkfc6Pgfm3mDzpeeFVEZM8YtTWH1GhWMnB8= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR13MB3786 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sync the logic from kernel driver, adjust the definition of structure, and extend the usage of nfp BAR from 8 to 24. This will greatly enhance the scalability of nfp PMD. Signed-off-by: Chaoyong He Reviewed-by: Niklas Söderlund --- drivers/net/nfp/nfp_ethdev.c | 8 +- drivers/net/nfp/nfpcore/nfp6000_pcie.c | 475 ++++++++++++++++++------- drivers/net/nfp/nfpcore/nfp6000_pcie.h | 1 + drivers/net/nfp/nfpcore/nfp_cpp.h | 5 +- drivers/net/nfp/nfpcore/nfp_cppcore.c | 2 +- 5 files changed, 346 insertions(+), 145 deletions(-) diff --git a/drivers/net/nfp/nfp_ethdev.c b/drivers/net/nfp/nfp_ethdev.c index 6eefec3836..d6454d8964 100644 --- a/drivers/net/nfp/nfp_ethdev.c +++ b/drivers/net/nfp/nfp_ethdev.c @@ -918,9 +918,9 @@ nfp_pf_init(struct rte_pci_device *pci_dev) * use a lock file if UIO is being used. */ if (pci_dev->kdrv == RTE_PCI_KDRV_VFIO) - cpp = nfp_cpp_from_nfp6000_pcie(pci_dev, false); + cpp = nfp_cpp_from_nfp6000_pcie(pci_dev, dev_info, false); else - cpp = nfp_cpp_from_nfp6000_pcie(pci_dev, true); + cpp = nfp_cpp_from_nfp6000_pcie(pci_dev, dev_info, true); if (cpp == NULL) { PMD_INIT_LOG(ERR, "A CPP handle can not be obtained"); @@ -1121,9 +1121,9 @@ nfp_pf_secondary_init(struct rte_pci_device *pci_dev) * use a lock file if UIO is being used. */ if (pci_dev->kdrv == RTE_PCI_KDRV_VFIO) - cpp = nfp_cpp_from_nfp6000_pcie(pci_dev, false); + cpp = nfp_cpp_from_nfp6000_pcie(pci_dev, dev_info, false); else - cpp = nfp_cpp_from_nfp6000_pcie(pci_dev, true); + cpp = nfp_cpp_from_nfp6000_pcie(pci_dev, dev_info, true); if (cpp == NULL) { PMD_INIT_LOG(ERR, "A CPP handle can not be obtained"); diff --git a/drivers/net/nfp/nfpcore/nfp6000_pcie.c b/drivers/net/nfp/nfpcore/nfp6000_pcie.c index e32ac1107c..c16d9474e2 100644 --- a/drivers/net/nfp/nfpcore/nfp6000_pcie.c +++ b/drivers/net/nfp/nfpcore/nfp6000_pcie.c @@ -19,6 +19,8 @@ #include #include +#include + #include "nfp_cpp.h" #include "nfp_logs.h" #include "nfp_target.h" @@ -59,20 +61,12 @@ #define NFP_PCIE_P2C_GENERAL_TOKEN_OFFSET(bar, x) ((x) << ((bar)->bitsize - 4)) #define NFP_PCIE_P2C_GENERAL_SIZE(bar) (1 << ((bar)->bitsize - 4)) -#define NFP_PCIE_CFG_BAR_PCIETOCPPEXPBAR(id, bar, slot) \ - (NFP_PCIE_BAR(id) + ((bar) * 8 + (slot)) * 4) - -#define NFP_PCIE_CPP_BAR_PCIETOCPPEXPBAR(bar, slot) \ - (((bar) * 8 + (slot)) * 4) +#define NFP_PCIE_P2C_EXPBAR_OFFSET(bar_index) ((bar_index) * 4) struct nfp_pcie_user; struct nfp6000_area_priv; /* Describes BAR configuration and usage */ -#define NFP_BAR_MIN 1 -#define NFP_BAR_MID 5 -#define NFP_BAR_MAX 7 - struct nfp_bar { struct nfp_pcie_user *nfp; /**< Backlink to owner */ uint32_t barcfg; /**< BAR config CSR */ @@ -80,22 +74,26 @@ struct nfp_bar { uint64_t mask; /**< Mask of the BAR aperture (read only) */ uint32_t bitsize; /**< Bit size of the BAR aperture (read only) */ uint32_t index; /**< Index of the BAR */ - int lock; /**< If the BAR has been locked */ + bool lock; /**< If the BAR has been locked */ - char *csr; char *iomem; /**< mapped IO memory */ + struct rte_mem_resource *resource; /**< IOMEM resource window */ }; -#define BUSDEV_SZ 13 +#define NFP_PCI_BAR_MAX (PCI_64BIT_BAR_COUNT * 8) + struct nfp_pcie_user { - struct nfp_bar bar[NFP_BAR_MAX]; + struct rte_pci_device *pci_dev; + const struct nfp_dev_info *dev_info; - int device; int lock; - char busdev[BUSDEV_SZ]; - int barsz; - int dev_id; - char *cfg; + + /* PCI BAR management */ + uint32_t bars; + struct nfp_bar bar[NFP_PCI_BAR_MAX]; + + /* Reserved BAR access */ + char *csr; }; /* Generic CPP bus access interface. */ @@ -206,19 +204,19 @@ nfp_bar_write(struct nfp_pcie_user *nfp, struct nfp_bar *bar, uint32_t newcfg) { - int base; - int slot; - - base = bar->index >> 3; - slot = bar->index & 7; + uint32_t xbar; - if (nfp->cfg == NULL) - return (-ENOMEM); + xbar = NFP_PCIE_P2C_EXPBAR_OFFSET(bar->index); - bar->csr = nfp->cfg + - NFP_PCIE_CFG_BAR_PCIETOCPPEXPBAR(nfp->dev_id, base, slot); - - *(uint32_t *)(bar->csr) = newcfg; + if (nfp->csr != NULL) { + rte_write32(newcfg, nfp->csr + xbar); + /* Readback to ensure BAR is flushed */ + rte_read32(nfp->csr + xbar); + } else { + xbar += nfp->dev_info->pcie_cfg_expbar_offset; + rte_pci_write_config(nfp->pci_dev, &newcfg, sizeof(uint32_t), + xbar); + } bar->barcfg = newcfg; @@ -249,105 +247,320 @@ nfp_reconfigure_bar(struct nfp_pcie_user *nfp, return nfp_bar_write(nfp, bar, newcfg); } -/* - * Map all PCI bars. We assume that the BAR with the PCIe config block is - * already mapped. +static uint32_t +nfp_bitsize_calc(uint64_t mask) +{ + uint64_t tmp = mask; + uint32_t bit_size = 0; + + if (tmp == 0) + return 0; + + for (; tmp != 0; tmp >>= 1) + bit_size++; + + return bit_size; +} + +static int +nfp_cmp_bars(const void *ptr_a, + const void *ptr_b) +{ + const struct nfp_bar *a = ptr_a; + const struct nfp_bar *b = ptr_b; + + if (a->bitsize == b->bitsize) + return a->index - b->index; + else + return a->bitsize - b->bitsize; +} + +static bool +nfp_bars_for_secondary(uint32_t index) +{ + uint8_t tmp = index & 0x07; + + if (tmp == 0x06 || tmp == 0x07) + return true; + else + return false; +} + +/** + * Map all PCI bars and fetch the actual BAR configurations from the board. + * We assume that the BAR with the PCIe config block is already mapped. * * BAR0.0: Reserved for General Mapping (for MSI-X access to PCIe SRAM) + * BAR0.1: -- + * BAR0.2: -- + * BAR0.3: -- + * BAR0.4: -- + * BAR0.5: -- + * BAR0.6: -- + * BAR0.7: -- * - * Halving PCItoCPPBars for primary and secondary processes. - * For CoreNIC firmware: - * NFP PMD just requires two fixed slots, one for configuration BAR, - * and another for accessing the hw queues. Another slot is needed - * for setting the link up or down. Secondary processes do not need - * to map the first two slots again, but it requires one slot for - * accessing the link, even if it is not likely the secondary process - * starting the port. - * For Flower firmware: - * NFP PMD need another fixed slots, used as the configureation BAR - * for ctrl vNIC. + * BAR1.0-BAR1.7: -- + * BAR2.0-BAR2.7: -- */ static int nfp_enable_bars(struct nfp_pcie_user *nfp) { - int x; - int end; - int start; + int pf; + uint32_t i; + uint8_t min_bars; struct nfp_bar *bar; + enum rte_proc_type_t type; + struct rte_mem_resource *res; + const uint32_t barcfg_msix_general = NFP_PCIE_BAR_PCIE2CPP_MAPTYPE + (NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_GENERAL) | + NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT_32BIT; + + type = rte_eal_process_type(); + if (type == RTE_PROC_PRIMARY) + min_bars = 12; + else + min_bars = 4; + + for (i = 0; i < RTE_DIM(nfp->bar); i++) { + if (i != 0) { + if (type == RTE_PROC_PRIMARY) { + if (nfp_bars_for_secondary(i)) + continue; + } else { + if (!nfp_bars_for_secondary(i)) + continue; + } + } - if (rte_eal_process_type() == RTE_PROC_PRIMARY) { - start = NFP_BAR_MID; - end = NFP_BAR_MIN; - } else { - start = NFP_BAR_MAX; - end = NFP_BAR_MID; + /* 24 NFP bars mapping into BAR0, BAR2 and BAR4 */ + res = &nfp->pci_dev->mem_resource[(i >> 3) * 2]; + + /* Skip over BARs that are not mapped */ + if (res->addr != NULL) { + bar = &nfp->bar[i]; + bar->resource = res; + bar->barcfg = 0; + + bar->nfp = nfp; + bar->index = i; + /* The resource shared by 8 bars */ + bar->mask = (res->len >> 3) - 1; + bar->bitsize = nfp_bitsize_calc(bar->mask); + bar->base = 0; + bar->lock = false; + bar->iomem = (char *)res->addr + + ((bar->index & 7) << bar->bitsize); + + nfp->bars++; + } } - for (x = start; x > end; x--) { - bar = &nfp->bar[x - 1]; - bar->barcfg = 0; - bar->nfp = nfp; - bar->index = x; - bar->mask = (1 << (nfp->barsz - 3)) - 1; - bar->bitsize = nfp->barsz - 3; - bar->base = 0; - bar->iomem = NULL; - bar->lock = 0; - bar->csr = nfp->cfg + NFP_PCIE_CFG_BAR_PCIETOCPPEXPBAR(nfp->dev_id, - bar->index >> 3, bar->index & 7); - bar->iomem = nfp->cfg + (bar->index << bar->bitsize); + if (nfp->bars < min_bars) { + PMD_DRV_LOG(ERR, "Not enough usable BARs found."); + return -EINVAL; } + + switch (nfp->pci_dev->id.device_id) { + case PCI_DEVICE_ID_NFP3800_PF_NIC: + pf = nfp->pci_dev->addr.function & 0x07; + nfp->csr = nfp->bar[0].iomem + NFP_PCIE_BAR(pf); + break; + case PCI_DEVICE_ID_NFP4000_PF_NIC: + case PCI_DEVICE_ID_NFP6000_PF_NIC: + nfp->csr = nfp->bar[0].iomem + NFP_PCIE_BAR(0); + break; + default: + PMD_DRV_LOG(ERR, "Unsupported device ID: %04hx!", + nfp->pci_dev->id.device_id); + return -EINVAL; + } + + /* Configure, and lock, BAR0.0 for General Target use (MSI-X SRAM) */ + bar = &nfp->bar[0]; + bar->lock = true; + + nfp_bar_write(nfp, bar, barcfg_msix_general); + + /* Sort bars by bit size - use the smallest possible first. */ + qsort(&nfp->bar[0], nfp->bars, sizeof(nfp->bar[0]), nfp_cmp_bars); + return 0; } -static struct nfp_bar * -nfp_alloc_bar(struct nfp_pcie_user *nfp) +/* Check if BAR can be used with the given parameters. */ +static bool +matching_bar_exist(struct nfp_bar *bar, + int target, + int action, + int token, + uint64_t offset, + size_t size, + int width) { - int x; - int end; - int start; - struct nfp_bar *bar; + int bar_width; + int bar_token; + int bar_target; + int bar_action; + uint32_t map_type; + + bar_width = NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT_OF(bar->barcfg); + switch (bar_width) { + case NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT_32BIT: + bar_width = 4; + break; + case NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT_64BIT: + bar_width = 8; + break; + case NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT_0BYTE: + bar_width = 0; + break; + default: + bar_width = -1; + break; + } - if (rte_eal_process_type() == RTE_PROC_PRIMARY) { - start = NFP_BAR_MID; - end = NFP_BAR_MIN; - } else { - start = NFP_BAR_MAX; - end = NFP_BAR_MID; + /* Make sure to match up the width */ + if (bar_width != width) + return false; + + bar_token = NFP_PCIE_BAR_PCIE2CPP_TOKEN_BASEADDRESS_OF(bar->barcfg); + bar_action = NFP_PCIE_BAR_PCIE2CPP_ACTION_BASEADDRESS_OF(bar->barcfg); + map_type = NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_OF(bar->barcfg); + switch (map_type) { + case NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_TARGET: + bar_token = -1; + /* FALLTHROUGH */ + case NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_BULK: + bar_action = NFP_CPP_ACTION_RW; + if (action == 0) + action = NFP_CPP_ACTION_RW; + /* FALLTHROUGH */ + case NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_FIXED: + break; + default: + /* We don't match explicit bars through the area interface */ + return false; } - for (x = start; x > end; x--) { - bar = &nfp->bar[x - 1]; - if (bar->lock == 0) { - bar->lock = 1; - return bar; - } + bar_target = NFP_PCIE_BAR_PCIE2CPP_TARGET_BASEADDRESS_OF(bar->barcfg); + if ((bar_target < 0 || bar_target == target) && + (bar_token < 0 || bar_token == token) && + bar_action == action && + bar->base <= offset && + (bar->base + (1 << bar->bitsize)) >= (offset + size)) + return true; + + /* No match */ + return false; +} + +static int +find_matching_bar(struct nfp_pcie_user *nfp, + int target, + int action, + int token, + uint64_t offset, + size_t size, + int width) +{ + uint32_t n; + + for (n = 0; n < nfp->bars; n++) { + struct nfp_bar *bar = &nfp->bar[n]; + + if (matching_bar_exist(bar, target, action, token, + offset, size, width)) + return n; + } + + return -1; +} + +/* Return EAGAIN if no resource is available */ +static int +find_unused_bar_noblock(struct nfp_pcie_user *nfp, + int target, + int action, + int token, + uint64_t offset, + size_t size, + int width) +{ + int ret; + uint32_t n; + const struct nfp_bar *bar; + + for (n = 0; n < nfp->bars; n++) { + bar = &nfp->bar[n]; + + if (bar->bitsize == 0) + continue; + + /* Just check to see if we can make it fit... */ + ret = nfp_compute_bar(bar, NULL, NULL, target, action, + token, offset, size, width); + if (ret != 0) + continue; + + if (!bar->lock) + return n; + } + + return -EAGAIN; +} + +static int +nfp_alloc_bar(struct nfp_pcie_user *nfp, + struct nfp6000_area_priv *priv) +{ + int ret; + int bar_num; + size_t size = priv->size; + int token = priv->token; + int target = priv->target; + int action = priv->action; + int width = priv->width.bar; + uint64_t offset = priv->offset; + + /* Bar size should small than 16MB */ + if (size > (1 << 24)) + return -EINVAL; + + bar_num = find_matching_bar(nfp, target, action, token, + offset, size, width); + if (bar_num >= 0) { + /* Found a perfect match. */ + nfp->bar[bar_num].lock = true; + return bar_num; } - return NULL; + bar_num = find_unused_bar_noblock(nfp, target, action, token, + offset, size, width); + if (bar_num < 0) + return bar_num; + + nfp->bar[bar_num].lock = true; + ret = nfp_reconfigure_bar(nfp, &nfp->bar[bar_num], + target, action, token, offset, size, width); + if (ret < 0) { + nfp->bar[bar_num].lock = false; + return ret; + } + + return bar_num; } static void nfp_disable_bars(struct nfp_pcie_user *nfp) { - int x; - int end; - int start; + uint32_t i; struct nfp_bar *bar; - if (rte_eal_process_type() == RTE_PROC_PRIMARY) { - start = NFP_BAR_MID; - end = NFP_BAR_MIN; - } else { - start = NFP_BAR_MAX; - end = NFP_BAR_MID; - } - - for (x = start; x > end; x--) { - bar = &nfp->bar[x - 1]; - if (bar->iomem) { + for (i = 0; i < nfp->bars; i++) { + bar = &nfp->bar[i]; + if (bar->iomem != NULL) { bar->iomem = NULL; - bar->lock = 0; + bar->lock = false; } } } @@ -364,7 +577,6 @@ nfp6000_area_init(struct nfp_cpp_area *area, uint32_t target = NFP_CPP_ID_TARGET_of(dest); uint32_t action = NFP_CPP_ID_ACTION_of(dest); struct nfp6000_area_priv *priv = nfp_cpp_area_priv(area); - struct nfp_pcie_user *nfp = nfp_cpp_priv(nfp_cpp_area_cpp(area)); pp = nfp_target_pushpull(NFP_CPP_ID(target, action, token), address); if (pp < 0) @@ -383,9 +595,7 @@ nfp6000_area_init(struct nfp_cpp_area *area, else priv->width.bar = priv->width.write; - priv->bar = nfp_alloc_bar(nfp); - if (priv->bar == NULL) - return -ENOMEM; + priv->bar = NULL; priv->target = target; priv->action = action; @@ -393,17 +603,29 @@ nfp6000_area_init(struct nfp_cpp_area *area, priv->offset = address; priv->size = size; - ret = nfp_reconfigure_bar(nfp, priv->bar, priv->target, priv->action, - priv->token, priv->offset, priv->size, - priv->width.bar); - return ret; } static int nfp6000_area_acquire(struct nfp_cpp_area *area) { + int bar_num; struct nfp6000_area_priv *priv = nfp_cpp_area_priv(area); + struct nfp_pcie_user *nfp = nfp_cpp_priv(nfp_cpp_area_cpp(area)); + + /* Already allocated. */ + if (priv->bar != NULL) + return 0; + + bar_num = nfp_alloc_bar(nfp, priv); + if (bar_num < 0) { + PMD_DRV_LOG(ERR, "Failed to allocate bar %d:%d:%d:%#lx: %d", + priv->target, priv->action, priv->token, + priv->offset, bar_num); + return bar_num; + } + + priv->bar = &nfp->bar[bar_num]; /* Calculate offset into BAR. */ if (nfp_bar_maptype(priv->bar) == @@ -432,7 +654,7 @@ nfp6000_area_release(struct nfp_cpp_area *area) { struct nfp6000_area_priv *priv = nfp_cpp_area_priv(area); - priv->bar->lock = 0; + priv->bar->lock = false; priv->bar = NULL; priv->iomem = NULL; } @@ -603,7 +825,8 @@ nfp_acquire_process_lock(struct nfp_pcie_user *desc) memset(&lock, 0, sizeof(lock)); - snprintf(lockname, sizeof(lockname), "/var/lock/nfp_%s", desc->busdev); + snprintf(lockname, sizeof(lockname), "/var/lock/nfp_%s", + desc->pci_dev->device.name); desc->lock = open(lockname, O_RDWR | O_CREAT, 0666); if (desc->lock < 0) return desc->lock; @@ -693,32 +916,11 @@ nfp6000_get_serial(struct rte_pci_device *dev, } static int -nfp6000_set_barsz(struct rte_pci_device *dev, - struct nfp_pcie_user *desc) -{ - int i = 0; - uint64_t tmp; - - tmp = dev->mem_resource[0].len; - - while (tmp >>= 1) - i++; - - desc->barsz = i; - - return 0; -} - -static int -nfp6000_init(struct nfp_cpp *cpp, - struct rte_pci_device *dev) +nfp6000_init(struct nfp_cpp *cpp) { int ret = 0; struct nfp_pcie_user *desc = nfp_cpp_priv(cpp); - memset(desc->busdev, 0, BUSDEV_SZ); - strlcpy(desc->busdev, dev->device.name, sizeof(desc->busdev)); - if (rte_eal_process_type() == RTE_PROC_PRIMARY && nfp_cpp_driver_need_lock(cpp)) { ret = nfp_acquire_process_lock(desc); @@ -726,12 +928,6 @@ nfp6000_init(struct nfp_cpp *cpp, return -1; } - if (nfp6000_set_barsz(dev, desc) < 0) - return -1; - - desc->cfg = dev->mem_resource[0].addr; - desc->dev_id = dev->addr.function & 0x7; - ret = nfp_enable_bars(desc); if (ret != 0) { PMD_DRV_LOG(ERR, "Enable bars failed"); @@ -749,7 +945,6 @@ nfp6000_free(struct nfp_cpp *cpp) nfp_disable_bars(desc); if (nfp_cpp_driver_need_lock(cpp)) close(desc->lock); - close(desc->device); rte_free(desc); } @@ -789,6 +984,7 @@ nfp_cpp_operations *nfp_cpp_transport_operations(void) */ struct nfp_cpp * nfp_cpp_from_nfp6000_pcie(struct rte_pci_device *pci_dev, + const struct nfp_dev_info *dev_info, bool driver_lock_needed) { int ret; @@ -800,6 +996,9 @@ nfp_cpp_from_nfp6000_pcie(struct rte_pci_device *pci_dev, if (nfp == NULL) return NULL; + nfp->pci_dev = pci_dev; + nfp->dev_info = dev_info; + ret = nfp6000_get_interface(pci_dev, &interface); if (ret != 0) { PMD_DRV_LOG(ERR, "Get interface failed."); diff --git a/drivers/net/nfp/nfpcore/nfp6000_pcie.h b/drivers/net/nfp/nfpcore/nfp6000_pcie.h index 8847f6f946..8e2cfb69e6 100644 --- a/drivers/net/nfp/nfpcore/nfp6000_pcie.h +++ b/drivers/net/nfp/nfpcore/nfp6000_pcie.h @@ -14,6 +14,7 @@ const struct nfp_cpp_operations *nfp_cpp_transport_operations(void); struct nfp_cpp *nfp_cpp_from_nfp6000_pcie(struct rte_pci_device *pci_dev, + const struct nfp_dev_info *dev_info, bool driver_lock_needed); #endif /* __NFP6000_PCIE_H__ */ diff --git a/drivers/net/nfp/nfpcore/nfp_cpp.h b/drivers/net/nfp/nfpcore/nfp_cpp.h index e879c7c920..2defc4fa16 100644 --- a/drivers/net/nfp/nfpcore/nfp_cpp.h +++ b/drivers/net/nfp/nfpcore/nfp_cpp.h @@ -18,6 +18,8 @@ struct nfp_cpp_area; #define NFP_CPP_NUM_TARGETS 16 +#define PCI_64BIT_BAR_COUNT 3 + /* * NFP CPP operations structure */ @@ -26,8 +28,7 @@ struct nfp_cpp_operations { size_t area_priv_size; /* Instance an NFP CPP */ - int (*init)(struct nfp_cpp *cpp, - struct rte_pci_device *dev); + int (*init)(struct nfp_cpp *cpp); /* * Free the bus. diff --git a/drivers/net/nfp/nfpcore/nfp_cppcore.c b/drivers/net/nfp/nfpcore/nfp_cppcore.c index 6f46dbf5b7..8a55670f84 100644 --- a/drivers/net/nfp/nfpcore/nfp_cppcore.c +++ b/drivers/net/nfp/nfpcore/nfp_cppcore.c @@ -947,7 +947,7 @@ nfp_cpp_alloc(struct rte_pci_device *pci_dev, * NOTE: cpp_lock is NOT locked for op->init, * since it may call NFP CPP API operations */ - err = cpp->op->init(cpp, pci_dev); + err = cpp->op->init(cpp); if (err < 0) { PMD_DRV_LOG(ERR, "NFP interface initialization failed"); rte_free(cpp);