From patchwork Tue Sep 5 11:21:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sivaramakrishnan Venkat X-Patchwork-Id: 131195 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 16A3442526; Wed, 6 Sep 2023 15:00:30 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A9D384027C; Wed, 6 Sep 2023 15:00:29 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id A7B4240289 for ; Tue, 5 Sep 2023 13:21:33 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693912893; x=1725448893; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=aXIU8rPamGWZkZVzZzztwwxehY40STD+2MvGzPYdVko=; b=RckCXHGoRC8XLHQXc2C9mY8ot8XAJILus/ub/lvRmxbhSUMFbBc9eOxf 41APFhwXnoh8G+7YBoDuGKxF68yVfnkCgk4qoYv7pN5qE1NzJlyeJENAz /5yoXvSoq4gTePxNGP+KsPiRV79u4KSwFN5vMqx8ZDAcl5AOgOjOCt17C dE3b+mfNO6Mz5p7U/oR43gOAoTRUbd+lqIFvoo4p8gFIxzny3C+xMYVaF /AxZY1owNEd0gdZGFDMBfT4VTXXq6++dJiny4HsAa5DI96hEBdXkKnv0v iYA+o50sshOhj4exlO9MGYCPaK4de5IAvYwHn688979CP6z1moy2cLyVJ Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10823"; a="374159146" X-IronPort-AV: E=Sophos;i="6.02,229,1688454000"; d="scan'208";a="374159146" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2023 04:21:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10823"; a="806567442" X-IronPort-AV: E=Sophos;i="6.02,229,1688454000"; d="scan'208";a="806567442" Received: from silpixa00401012.ir.intel.com ([10.243.23.140]) by fmsmga008.fm.intel.com with ESMTP; 05 Sep 2023 04:21:30 -0700 From: Sivaramakrishnan VenkatX To: Kai Ji Cc: dev@dpdk.org, Sivaramakrishnan VenkatX Subject: [PATCH v2] drivers/crypto: cipher buffer alignment check Date: Tue, 5 Sep 2023 11:21:25 +0000 Message-Id: <20230905112125.5735-1-venkatx.sivaramakrishnan@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230822104610.954234-1-venkatx.sivaramakrishnan@intel.com> References: <20230822104610.954234-1-venkatx.sivaramakrishnan@intel.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 06 Sep 2023 15:00:28 +0200 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Cipher length alignment checked for 3DES-CBC and AES-CBC to avoid slice hang error in QAT CPM1.8 Signed-off-by: Sivaramakrishnan VenkatX Acked-by: Ciara Power Signed-off-by: Sivaramakrishnan Venkat --- V2: Set auth_length = 0 for NULL CIPHER NULL AUTH operation. --- drivers/crypto/qat/dev/qat_crypto_pmd_gens.h | 22 ++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h index cab7e214c0..37647374d5 100644 --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h @@ -10,6 +10,13 @@ #include "qat_sym_session.h" #include "qat_sym.h" +#define AES_OR_3DES_MISALIGNED (ctx->qat_mode == ICP_QAT_HW_CIPHER_CBC_MODE && \ + ((((ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES128) || \ + (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES192) || \ + (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES256)) && \ + (cipher_param->cipher_length % ICP_QAT_HW_AES_BLK_SZ)) || \ + ((ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_3DES) && \ + (cipher_param->cipher_length % ICP_QAT_HW_3DES_BLK_SZ)))) #define QAT_SYM_DP_GET_MAX_ENQ(q, c, n) \ RTE_MIN((q->max_inflights - q->enqueued + q->dequeued - c), n) @@ -704,6 +711,21 @@ enqueue_one_chain_job_gen1(struct qat_sym_session *ctx, auth_param->auth_off = ofs.ofs.auth.head; auth_param->auth_len = auth_len; auth_param->auth_res_addr = digest->iova; + /* Input cipher length alignment requirement for 3DES-CBC and AES-CBC. + * For 3DES-CBC cipher algo, ESP Payload size requires 8 Byte aligned. + * For AES-CBC cipher algo, ESP Payload size requires 16 Byte aligned. + * The alignment should be guaranteed by the ESP package padding field + * according to the RFC4303. Under this condition, QAT will pass through + * chain job as NULL cipher and NULL auth operation and report misalignment + * error detected. + */ + if (AES_OR_3DES_MISALIGNED) { + QAT_LOG(ERR, "Input cipher length alignment error detected.\n"); + ctx->qat_cipher_alg = ICP_QAT_HW_CIPHER_ALGO_NULL; + ctx->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL; + cipher_param->cipher_length = 0; + auth_param->auth_len = 0; + } switch (ctx->qat_hash_alg) { case ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2: