From patchwork Mon Sep 18 02:11:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simei Su X-Patchwork-Id: 131530 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7CF77425C9; Mon, 18 Sep 2023 04:13:17 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EE2E040DCB; Mon, 18 Sep 2023 04:12:45 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 81E5640A81 for ; Mon, 18 Sep 2023 04:12:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695003159; x=1726539159; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=t1YwhA6ODp7Rx/kepctuEro/dp+EeLR0ibMpoGVGNDQ=; b=ZKwb78kc9LnQ1mpjLyV7915bh35rw/9xli+98yjz7UvWSRULNu21MN74 9Ad/CMR1HEI1USPFJq2ogxeJSN/SimMM+0DftViPQHx4aYGjQyP6RYAje HyDw9tKlTwbEeBJy4tSmF6rZ8jay3T3JijiPnmrepnoaT1R6KozV0KRAy cVpIqQnnWVRRzp6p9ShrSfkgoylNOLhTm8ENN7NuOrUjTE0dJbaIQGgL9 3r+J/HqPymGm7lUYxbqO7Wimn74frTaeZUouHVOsAKt8+t60bUNzfOpFJ l11crnCGnN9o44Uh5S7IFuf6aQX/hWV+aRvTH8mU/xM7N6cvrK0j7rd2p g==; X-IronPort-AV: E=McAfee;i="6600,9927,10836"; a="359801764" X-IronPort-AV: E=Sophos;i="6.02,155,1688454000"; d="scan'208";a="359801764" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Sep 2023 19:11:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10836"; a="815847024" X-IronPort-AV: E=Sophos;i="6.02,155,1688454000"; d="scan'208";a="815847024" Received: from dpdk-simei-icelake.sh.intel.com ([10.67.110.167]) by fmsmga004.fm.intel.com with ESMTP; 17 Sep 2023 19:11:38 -0700 From: Simei Su To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, wenjun1.wu@intel.com, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Pavan Kumar Linga Subject: [PATCH v4 14/18] common/idpf/base: use GENMASK macro Date: Mon, 18 Sep 2023 10:11:26 +0800 Message-Id: <20230918021130.192982-15-simei.su@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230918021130.192982-1-simei.su@intel.com> References: <20230915021730.2681882-1-simei.su@intel.com> <20230918021130.192982-1-simei.su@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Instead of using a custom defined macro for generating a mask, use the standard GENMASK macro. Signed-off-by: Pavan Kumar Linga Signed-off-by: Simei Su Acked-by: Beilei Xing --- drivers/common/idpf/base/idpf_lan_pf_regs.h | 26 ++--- drivers/common/idpf/base/idpf_lan_txrx.h | 116 +++++++++----------- drivers/common/idpf/base/idpf_lan_vf_regs.h | 16 +-- drivers/common/idpf/base/idpf_osdep.h | 7 ++ 4 files changed, 80 insertions(+), 85 deletions(-) diff --git a/drivers/common/idpf/base/idpf_lan_pf_regs.h b/drivers/common/idpf/base/idpf_lan_pf_regs.h index e47afad6e9..b9d82592c0 100644 --- a/drivers/common/idpf/base/idpf_lan_pf_regs.h +++ b/drivers/common/idpf/base/idpf_lan_pf_regs.h @@ -24,7 +24,7 @@ #define PF_FW_ARQBAH (PF_FW_BASE + 0x4) #define PF_FW_ARQLEN (PF_FW_BASE + 0x8) #define PF_FW_ARQLEN_ARQLEN_S 0 -#define PF_FW_ARQLEN_ARQLEN_M IDPF_M(0x1FFF, PF_FW_ARQLEN_ARQLEN_S) +#define PF_FW_ARQLEN_ARQLEN_M GENMASK(12, 0) #define PF_FW_ARQLEN_ARQVFE_S 28 #define PF_FW_ARQLEN_ARQVFE_M BIT(PF_FW_ARQLEN_ARQVFE_S) #define PF_FW_ARQLEN_ARQOVFL_S 29 @@ -35,14 +35,14 @@ #define PF_FW_ARQLEN_ARQENABLE_M BIT(PF_FW_ARQLEN_ARQENABLE_S) #define PF_FW_ARQH (PF_FW_BASE + 0xC) #define PF_FW_ARQH_ARQH_S 0 -#define PF_FW_ARQH_ARQH_M IDPF_M(0x1FFF, PF_FW_ARQH_ARQH_S) +#define PF_FW_ARQH_ARQH_M GENMASK(12, 0) #define PF_FW_ARQT (PF_FW_BASE + 0x10) #define PF_FW_ATQBAL (PF_FW_BASE + 0x14) #define PF_FW_ATQBAH (PF_FW_BASE + 0x18) #define PF_FW_ATQLEN (PF_FW_BASE + 0x1C) #define PF_FW_ATQLEN_ATQLEN_S 0 -#define PF_FW_ATQLEN_ATQLEN_M IDPF_M(0x3FF, PF_FW_ATQLEN_ATQLEN_S) +#define PF_FW_ATQLEN_ATQLEN_M GENMASK(9, 0) #define PF_FW_ATQLEN_ATQVFE_S 28 #define PF_FW_ATQLEN_ATQVFE_M BIT(PF_FW_ATQLEN_ATQVFE_S) #define PF_FW_ATQLEN_ATQOVFL_S 29 @@ -53,7 +53,7 @@ #define PF_FW_ATQLEN_ATQENABLE_M BIT(PF_FW_ATQLEN_ATQENABLE_S) #define PF_FW_ATQH (PF_FW_BASE + 0x20) #define PF_FW_ATQH_ATQH_S 0 -#define PF_FW_ATQH_ATQH_M IDPF_M(0x3FF, PF_FW_ATQH_ATQH_S) +#define PF_FW_ATQH_ATQH_M GENMASK(9, 0) #define PF_FW_ATQT (PF_FW_BASE + 0x24) /* Interrupts */ @@ -66,7 +66,7 @@ #define PF_GLINT_DYN_CTL_SWINT_TRIG_S 2 #define PF_GLINT_DYN_CTL_SWINT_TRIG_M BIT(PF_GLINT_DYN_CTL_SWINT_TRIG_S) #define PF_GLINT_DYN_CTL_ITR_INDX_S 3 -#define PF_GLINT_DYN_CTL_ITR_INDX_M IDPF_M(0x3, PF_GLINT_DYN_CTL_ITR_INDX_S) +#define PF_GLINT_DYN_CTL_ITR_INDX_M GENMASK(4, 3) #define PF_GLINT_DYN_CTL_INTERVAL_S 5 #define PF_GLINT_DYN_CTL_INTERVAL_M BIT(PF_GLINT_DYN_CTL_INTERVAL_S) #define PF_GLINT_DYN_CTL_SW_ITR_INDX_ENA_S 24 @@ -87,13 +87,13 @@ (PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) * 0x1000)) #define PF_GLINT_ITR_MAX_INDEX 2 #define PF_GLINT_ITR_INTERVAL_S 0 -#define PF_GLINT_ITR_INTERVAL_M IDPF_M(0xFFF, PF_GLINT_ITR_INTERVAL_S) +#define PF_GLINT_ITR_INTERVAL_M GENMASK(11, 0) /* Timesync registers */ #define PF_TIMESYNC_BASE 0x08404000 #define PF_GLTSYN_CMD_SYNC (PF_TIMESYNC_BASE) #define PF_GLTSYN_CMD_SYNC_EXEC_CMD_S 0 -#define PF_GLTSYN_CMD_SYNC_EXEC_CMD_M IDPF_M(0x3, PF_GLTSYN_CMD_SYNC_EXEC_CMD_S) +#define PF_GLTSYN_CMD_SYNC_EXEC_CMD_M GENMASK(1, 0) #define PF_GLTSYN_CMD_SYNC_SHTIME_EN_S 2 #define PF_GLTSYN_CMD_SYNC_SHTIME_EN_M BIT(PF_GLTSYN_CMD_SYNC_SHTIME_EN_S) #define PF_GLTSYN_SHTIME_0 (PF_TIMESYNC_BASE + 0x4) @@ -105,23 +105,23 @@ /* Generic registers */ #define PF_INT_DIR_OICR_ENA 0x08406000 #define PF_INT_DIR_OICR_ENA_S 0 -#define PF_INT_DIR_OICR_ENA_M IDPF_M(0xFFFFFFFF, PF_INT_DIR_OICR_ENA_S) +#define PF_INT_DIR_OICR_ENA_M GENMASK(31, 0) #define PF_INT_DIR_OICR 0x08406004 #define PF_INT_DIR_OICR_TSYN_EVNT 0 #define PF_INT_DIR_OICR_PHY_TS_0 BIT(1) #define PF_INT_DIR_OICR_PHY_TS_1 BIT(2) #define PF_INT_DIR_OICR_CAUSE 0x08406008 #define PF_INT_DIR_OICR_CAUSE_CAUSE_S 0 -#define PF_INT_DIR_OICR_CAUSE_CAUSE_M IDPF_M(0xFFFFFFFF, PF_INT_DIR_OICR_CAUSE_CAUSE_S) +#define PF_INT_DIR_OICR_CAUSE_CAUSE_M GENMASK(31, 0) #define PF_INT_PBA_CLEAR 0x0840600C #define PF_FUNC_RID 0x08406010 #define PF_FUNC_RID_FUNCTION_NUMBER_S 0 -#define PF_FUNC_RID_FUNCTION_NUMBER_M IDPF_M(0x7, PF_FUNC_RID_FUNCTION_NUMBER_S) +#define PF_FUNC_RID_FUNCTION_NUMBER_M GENMASK(2, 0) #define PF_FUNC_RID_DEVICE_NUMBER_S 3 -#define PF_FUNC_RID_DEVICE_NUMBER_M IDPF_M(0x1F, PF_FUNC_RID_DEVICE_NUMBER_S) +#define PF_FUNC_RID_DEVICE_NUMBER_M GENMASK(7, 3) #define PF_FUNC_RID_BUS_NUMBER_S 8 -#define PF_FUNC_RID_BUS_NUMBER_M IDPF_M(0xFF, PF_FUNC_RID_BUS_NUMBER_S) +#define PF_FUNC_RID_BUS_NUMBER_M GENMASK(15, 8) /* Reset registers */ #define PFGEN_RTRIG 0x08407000 @@ -133,7 +133,7 @@ #define PFGEN_RTRIG_IMCR_M BIT(2) #define PFGEN_RSTAT 0x08407008 /* PFR Status */ #define PFGEN_RSTAT_PFR_STATE_S 0 -#define PFGEN_RSTAT_PFR_STATE_M IDPF_M(0x3, PFGEN_RSTAT_PFR_STATE_S) +#define PFGEN_RSTAT_PFR_STATE_M GENMASK(1, 0) #define PFGEN_CTRL 0x0840700C #define PFGEN_CTRL_PFSWR BIT(0) diff --git a/drivers/common/idpf/base/idpf_lan_txrx.h b/drivers/common/idpf/base/idpf_lan_txrx.h index 4951e266f0..f213c49e47 100644 --- a/drivers/common/idpf/base/idpf_lan_txrx.h +++ b/drivers/common/idpf/base/idpf_lan_txrx.h @@ -60,65 +60,54 @@ enum idpf_rss_hash { BIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV6_UDP)) /* For idpf_splitq_base_tx_compl_desc */ -#define IDPF_TXD_COMPLQ_GEN_S 15 +#define IDPF_TXD_COMPLQ_GEN_S 15 #define IDPF_TXD_COMPLQ_GEN_M BIT_ULL(IDPF_TXD_COMPLQ_GEN_S) #define IDPF_TXD_COMPLQ_COMPL_TYPE_S 11 -#define IDPF_TXD_COMPLQ_COMPL_TYPE_M \ - IDPF_M(0x7UL, IDPF_TXD_COMPLQ_COMPL_TYPE_S) -#define IDPF_TXD_COMPLQ_QID_S 0 -#define IDPF_TXD_COMPLQ_QID_M IDPF_M(0x3FFUL, IDPF_TXD_COMPLQ_QID_S) +#define IDPF_TXD_COMPLQ_COMPL_TYPE_M GENMASK_ULL(13, 11) +#define IDPF_TXD_COMPLQ_QID_S 0 +#define IDPF_TXD_COMPLQ_QID_M GENMASK_ULL(9, 0) /* For base mode TX descriptors */ -#define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S 23 -#define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_M BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S) -#define IDPF_TXD_CTX_QW0_TUNN_DECTTL_S 19 -#define IDPF_TXD_CTX_QW0_TUNN_DECTTL_M \ - (0xFULL << IDPF_TXD_CTX_QW0_TUNN_DECTTL_S) -#define IDPF_TXD_CTX_QW0_TUNN_NATLEN_S 12 -#define IDPF_TXD_CTX_QW0_TUNN_NATLEN_M \ - (0X7FULL << IDPF_TXD_CTX_QW0_TUNN_NATLEN_S) +#define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S 23 +#define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_M \ + BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S) +#define IDPF_TXD_CTX_QW0_TUNN_DECTTL_S 19 +#define IDPF_TXD_CTX_QW0_TUNN_DECTTL_M GENMASK_ULL(22, 19) +#define IDPF_TXD_CTX_QW0_TUNN_NATLEN_S 12 +#define IDPF_TXD_CTX_QW0_TUNN_NATLEN_M GENMASK_ULL(18, 12) #define IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_S 11 -#define IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_M \ +#define IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_M \ BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_S) #define IDPF_TXD_CTX_EIP_NOINC_IPID_CONST \ IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_M -#define IDPF_TXD_CTX_QW0_TUNN_NATT_S 9 -#define IDPF_TXD_CTX_QW0_TUNN_NATT_M (0x3ULL << IDPF_TXD_CTX_QW0_TUNN_NATT_S) -#define IDPF_TXD_CTX_UDP_TUNNELING BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_NATT_S) -#define IDPF_TXD_CTX_GRE_TUNNELING (0x2ULL << IDPF_TXD_CTX_QW0_TUNN_NATT_S) +#define IDPF_TXD_CTX_QW0_TUNN_NATT_S 9 +#define IDPF_TXD_CTX_QW0_TUNN_NATT_M GENMASK_ULL(10, 9) +#define IDPF_TXD_CTX_UDP_TUNNELING BIT_ULL(9) +#define IDPF_TXD_CTX_GRE_TUNNELING BIT_ULL(10) #define IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_S 2 -#define IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_M \ - (0x3FULL << IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_S) -#define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_S 0 -#define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_M \ - (0x3ULL << IDPF_TXD_CTX_QW0_TUNN_EXT_IP_S) - -#define IDPF_TXD_CTX_QW1_MSS_S 50 -#define IDPF_TXD_CTX_QW1_MSS_M \ - IDPF_M(0x3FFFULL, IDPF_TXD_CTX_QW1_MSS_S) -#define IDPF_TXD_CTX_QW1_TSO_LEN_S 30 -#define IDPF_TXD_CTX_QW1_TSO_LEN_M \ - IDPF_M(0x3FFFFULL, IDPF_TXD_CTX_QW1_TSO_LEN_S) -#define IDPF_TXD_CTX_QW1_CMD_S 4 -#define IDPF_TXD_CTX_QW1_CMD_M \ - IDPF_M(0xFFFUL, IDPF_TXD_CTX_QW1_CMD_S) -#define IDPF_TXD_CTX_QW1_DTYPE_S 0 -#define IDPF_TXD_CTX_QW1_DTYPE_M \ - IDPF_M(0xFUL, IDPF_TXD_CTX_QW1_DTYPE_S) -#define IDPF_TXD_QW1_L2TAG1_S 48 -#define IDPF_TXD_QW1_L2TAG1_M \ - IDPF_M(0xFFFFULL, IDPF_TXD_QW1_L2TAG1_S) -#define IDPF_TXD_QW1_TX_BUF_SZ_S 34 -#define IDPF_TXD_QW1_TX_BUF_SZ_M \ - IDPF_M(0x3FFFULL, IDPF_TXD_QW1_TX_BUF_SZ_S) -#define IDPF_TXD_QW1_OFFSET_S 16 -#define IDPF_TXD_QW1_OFFSET_M \ - IDPF_M(0x3FFFFULL, IDPF_TXD_QW1_OFFSET_S) -#define IDPF_TXD_QW1_CMD_S 4 -#define IDPF_TXD_QW1_CMD_M IDPF_M(0xFFFUL, IDPF_TXD_QW1_CMD_S) -#define IDPF_TXD_QW1_DTYPE_S 0 -#define IDPF_TXD_QW1_DTYPE_M IDPF_M(0xFUL, IDPF_TXD_QW1_DTYPE_S) +#define IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_M GENMASK_ULL(7, 2) +#define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_S 0 +#define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_M GENMASK_ULL(1, 0) + +#define IDPF_TXD_CTX_QW1_MSS_S 50 +#define IDPF_TXD_CTX_QW1_MSS_M GENMASK_ULL(63, 50) +#define IDPF_TXD_CTX_QW1_TSO_LEN_S 30 +#define IDPF_TXD_CTX_QW1_TSO_LEN_M GENMASK_ULL(47, 30) +#define IDPF_TXD_CTX_QW1_CMD_S 4 +#define IDPF_TXD_CTX_QW1_CMD_M GENMASK_ULL(15, 4) +#define IDPF_TXD_CTX_QW1_DTYPE_S 0 +#define IDPF_TXD_CTX_QW1_DTYPE_M GENMASK_ULL(3, 0) +#define IDPF_TXD_QW1_L2TAG1_S 48 +#define IDPF_TXD_QW1_L2TAG1_M GENMASK_ULL(63, 48) +#define IDPF_TXD_QW1_TX_BUF_SZ_S 34 +#define IDPF_TXD_QW1_TX_BUF_SZ_M GENMASK_ULL(47, 34) +#define IDPF_TXD_QW1_OFFSET_S 16 +#define IDPF_TXD_QW1_OFFSET_M GENMASK_ULL(33, 16) +#define IDPF_TXD_QW1_CMD_S 4 +#define IDPF_TXD_QW1_CMD_M GENMASK_ULL(15, 4) +#define IDPF_TXD_QW1_DTYPE_S 0 +#define IDPF_TXD_QW1_DTYPE_M GENMASK_ULL(3, 0) /* TX Completion Descriptor Completion Types */ #define IDPF_TXD_COMPLT_ITR_FLUSH 0 @@ -169,10 +158,10 @@ enum idpf_tx_desc_len_fields { IDPF_TX_DESC_LEN_L4_LEN_S = 14 /* 4 BITS */ }; -#define IDPF_TXD_QW1_MACLEN_M IDPF_M(0x7FUL, IDPF_TX_DESC_LEN_MACLEN_S) -#define IDPF_TXD_QW1_IPLEN_M IDPF_M(0x7FUL, IDPF_TX_DESC_LEN_IPLEN_S) -#define IDPF_TXD_QW1_L4LEN_M IDPF_M(0xFUL, IDPF_TX_DESC_LEN_L4_LEN_S) -#define IDPF_TXD_QW1_FCLEN_M IDPF_M(0xFUL, IDPF_TX_DESC_LEN_L4_LEN_S) +#define IDPF_TXD_QW1_MACLEN_M GENMASK_ULL(6, 0) +#define IDPF_TXD_QW1_IPLEN_M GENMASK_ULL(13, 7) +#define IDPF_TXD_QW1_L4LEN_M GENMASK_ULL(17, 14) +#define IDPF_TXD_QW1_FCLEN_M GENMASK_ULL(17, 14) enum idpf_tx_base_desc_cmd_bits { IDPF_TX_DESC_CMD_EOP = 0x0001, @@ -238,11 +227,10 @@ struct idpf_flex_tx_desc { __le64 buf_addr; /* Packet buffer address */ struct { __le16 cmd_dtype; -#define IDPF_FLEX_TXD_QW1_DTYPE_S 0 -#define IDPF_FLEX_TXD_QW1_DTYPE_M \ - IDPF_M(0x1FUL, IDPF_FLEX_TXD_QW1_DTYPE_S) +#define IDPF_FLEX_TXD_QW1_DTYPE_S 0 +#define IDPF_FLEX_TXD_QW1_DTYPE_M GENMASK(4, 0) #define IDPF_FLEX_TXD_QW1_CMD_S 5 -#define IDPF_FLEX_TXD_QW1_CMD_M IDPF_M(0x7FFUL, IDPF_TXD_QW1_CMD_S) +#define IDPF_FLEX_TXD_QW1_CMD_M GENMASK(15, 5) union { /* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_DATA_(0x03) */ u8 raw[4]; @@ -384,9 +372,9 @@ struct idpf_flex_tx_hs_ctx_desc { #define IDPF_TXD_FLEX_CTX_MSS_RT_0 0 #define IDPF_TXD_FLEX_CTX_MSS_RT_M 0x3FFF #define IDPF_TXD_FLEX_CTX_FTYPE_S 14 -#define IDPF_TXD_FLEX_CTX_FTYPE_VF IDPF_M(0x0, IDPF_TXD_FLEX_CTX_FTYPE_S) -#define IDPF_TXD_FLEX_CTX_FTYPE_VDEV IDPF_M(0x1, IDPF_TXD_FLEX_CTX_FTYPE_S) -#define IDPF_TXD_FLEX_CTX_FTYPE_PF IDPF_M(0x2, IDPF_TXD_FLEX_CTX_FTYPE_S) +#define IDPF_TXD_FLEX_CTX_FTYPE_VF 0 +#define IDPF_TXD_FLEX_CTX_FTYPE_VDEV BIT(14) +#define IDPF_TXD_FLEX_CTX_FTYPE_PF BIT(15) u8 hdr_len; u8 ptag; } tso; @@ -403,10 +391,10 @@ struct idpf_flex_tx_hs_ctx_desc { #define IDPF_TXD_FLEX_CTX_QW1_PASID_M 0xFFFFF #define IDPF_TXD_FLEX_CTX_QW1_PASID_VALID_S 36 #define IDPF_TXD_FLEX_CTX_QW1_PASID_VALID \ - IDPF_M(0x1, IDPF_TXD_FLEX_CTX_PASID_VALID_S) + BIT_ULL(IDPF_TXD_FLEX_CTX_QW1_PASID_VALID_S) #define IDPF_TXD_FLEX_CTX_QW1_TPH_S 37 -#define IDPF_TXD_FLEX_CTX_QW1_TPH \ - IDPF_M(0x1, IDPF_TXD_FLEX_CTX_TPH_S) +#define IDPF_TXD_FLEX_CTX_QW1_TPH \ + BIT_ULL(IDPF_TXD_FLEX_CTX_QW1_TPH_S) #define IDPF_TXD_FLEX_CTX_QW1_PFNUM_S 38 #define IDPF_TXD_FLEX_CTX_QW1_PFNUM_M 0xF /* The following are only valid for DTYPE = 0x09 and DTYPE = 0x0A */ @@ -414,7 +402,7 @@ struct idpf_flex_tx_hs_ctx_desc { #define IDPF_TXD_FLEX_CTX_QW1_SAIDX_M 0x1FFFFF #define IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S 63 #define IDPF_TXD_FLEX_CTX_QW1_SAIDX_VALID \ - IDPF_M(0x1, IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S) + BIT_ULL(IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S) /* The following are only valid for DTYPE = 0x0D and DTYPE = 0x0E */ #define IDPF_TXD_FLEX_CTX_QW1_FLEX0_S 48 #define IDPF_TXD_FLEX_CTX_QW1_FLEX0_M 0xFF diff --git a/drivers/common/idpf/base/idpf_lan_vf_regs.h b/drivers/common/idpf/base/idpf_lan_vf_regs.h index 4c5249129e..f394a0d67a 100644 --- a/drivers/common/idpf/base/idpf_lan_vf_regs.h +++ b/drivers/common/idpf/base/idpf_lan_vf_regs.h @@ -9,7 +9,7 @@ /* Reset */ #define VFGEN_RSTAT 0x00008800 #define VFGEN_RSTAT_VFR_STATE_S 0 -#define VFGEN_RSTAT_VFR_STATE_M IDPF_M(0x3, VFGEN_RSTAT_VFR_STATE_S) +#define VFGEN_RSTAT_VFR_STATE_M GENMASK(1, 0) /* Control(VF Mailbox) Queue */ #define VF_BASE 0x00006000 @@ -18,7 +18,7 @@ #define VF_ATQBAH (VF_BASE + 0x1800) #define VF_ATQLEN (VF_BASE + 0x0800) #define VF_ATQLEN_ATQLEN_S 0 -#define VF_ATQLEN_ATQLEN_M IDPF_M(0x3FF, VF_ATQLEN_ATQLEN_S) +#define VF_ATQLEN_ATQLEN_M GENMASK(9, 0) #define VF_ATQLEN_ATQVFE_S 28 #define VF_ATQLEN_ATQVFE_M BIT(VF_ATQLEN_ATQVFE_S) #define VF_ATQLEN_ATQOVFL_S 29 @@ -29,14 +29,14 @@ #define VF_ATQLEN_ATQENABLE_M BIT(VF_ATQLEN_ATQENABLE_S) #define VF_ATQH (VF_BASE + 0x0400) #define VF_ATQH_ATQH_S 0 -#define VF_ATQH_ATQH_M IDPF_M(0x3FF, VF_ATQH_ATQH_S) +#define VF_ATQH_ATQH_M GENMASK(9, 0) #define VF_ATQT (VF_BASE + 0x2400) #define VF_ARQBAL (VF_BASE + 0x0C00) #define VF_ARQBAH (VF_BASE) #define VF_ARQLEN (VF_BASE + 0x2000) #define VF_ARQLEN_ARQLEN_S 0 -#define VF_ARQLEN_ARQLEN_M IDPF_M(0x3FF, VF_ARQLEN_ARQLEN_S) +#define VF_ARQLEN_ARQLEN_M GENMASK(9, 0) #define VF_ARQLEN_ARQVFE_S 28 #define VF_ARQLEN_ARQVFE_M BIT(VF_ARQLEN_ARQVFE_S) #define VF_ARQLEN_ARQOVFL_S 29 @@ -47,7 +47,7 @@ #define VF_ARQLEN_ARQENABLE_M BIT(VF_ARQLEN_ARQENABLE_S) #define VF_ARQH (VF_BASE + 0x1400) #define VF_ARQH_ARQH_S 0 -#define VF_ARQH_ARQH_M IDPF_M(0x1FFF, VF_ARQH_ARQH_S) +#define VF_ARQH_ARQH_M GENMASK(12, 0) #define VF_ARQT (VF_BASE + 0x1000) /* Transmit queues */ @@ -69,7 +69,7 @@ #define VF_INT_DYN_CTL0_INTENA_S 0 #define VF_INT_DYN_CTL0_INTENA_M BIT(VF_INT_DYN_CTL0_INTENA_S) #define VF_INT_DYN_CTL0_ITR_INDX_S 3 -#define VF_INT_DYN_CTL0_ITR_INDX_M IDPF_M(0x3, VF_INT_DYN_CTL0_ITR_INDX_S) +#define VF_INT_DYN_CTL0_ITR_INDX_M GENMASK(4, 3) #define VF_INT_DYN_CTLN(_INT) (0x00003800 + ((_INT) * 4)) #define VF_INT_DYN_CTLN_EXT(_INT) (0x00070000 + ((_INT) * 4)) #define VF_INT_DYN_CTLN_INTENA_S 0 @@ -79,7 +79,7 @@ #define VF_INT_DYN_CTLN_SWINT_TRIG_S 2 #define VF_INT_DYN_CTLN_SWINT_TRIG_M BIT(VF_INT_DYN_CTLN_SWINT_TRIG_S) #define VF_INT_DYN_CTLN_ITR_INDX_S 3 -#define VF_INT_DYN_CTLN_ITR_INDX_M IDPF_M(0x3, VF_INT_DYN_CTLN_ITR_INDX_S) +#define VF_INT_DYN_CTLN_ITR_INDX_M GENMASK(4, 3) #define VF_INT_DYN_CTLN_INTERVAL_S 5 #define VF_INT_DYN_CTLN_INTERVAL_M BIT(VF_INT_DYN_CTLN_INTERVAL_S) #define VF_INT_DYN_CTLN_SW_ITR_INDX_ENA_S 24 @@ -113,7 +113,7 @@ (0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000)) #define VF_INT_ITRN_MAX_INDEX 2 #define VF_INT_ITRN_INTERVAL_S 0 -#define VF_INT_ITRN_INTERVAL_M IDPF_M(0xFFF, VF_INT_ITRN_INTERVAL_S) +#define VF_INT_ITRN_INTERVAL_M GENMASK(11, 0) #define VF_INT_PBA_CLEAR 0x00008900 #define VF_INT_ICR0_ENA1 0x00005000 diff --git a/drivers/common/idpf/base/idpf_osdep.h b/drivers/common/idpf/base/idpf_osdep.h index 2a817a9807..74a376cb13 100644 --- a/drivers/common/idpf/base/idpf_osdep.h +++ b/drivers/common/idpf/base/idpf_osdep.h @@ -48,6 +48,13 @@ typedef struct idpf_lock idpf_lock; #define IDPF_M(m, s) ((m) << (s)) +#define BITS_PER_LONG (8 * sizeof(long)) +#define BITS_PER_LONG_LONG (8 * sizeof(long long)) +#define GENMASK(h, l) \ + (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) +#define GENMASK_ULL(h, l) \ + (((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) + #ifndef ETH_ADDR_LEN #define ETH_ADDR_LEN 6 #endif