From patchwork Fri Sep 29 18:13:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 132238 X-Patchwork-Delegate: maxime.coquelin@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4263142677; Fri, 29 Sep 2023 22:15:58 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3C8CC402EC; Fri, 29 Sep 2023 22:15:44 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by mails.dpdk.org (Postfix) with ESMTP id 751344026E for ; Fri, 29 Sep 2023 22:15:40 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1696018541; x=1727554541; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LQExTWvJXGZMt/hJLoy7mJ4n4AD8JzyVilQ6T14Jdh4=; b=Gy7SWVlnr2YZbh2qlqdHEHXHiCL//s5wfZp65ivTtmckUYJAz6I/ae5Z +99PT/eb+kD2D0hDU1xHQIfLYhDwoOc6TDdfFpH3GufdZNatVmDZhscw1 uWSf1WKniSHS1r8mmGrb2KMvY80dhWqnFIsRuY8K20zEOUgDM8ZHAuTZm oa7mygj0MDHBr5xxPGAzIxZya3Y7oQfllHL0XkZgwo6aQXThRwsNTtAMj TU8M67PT1XaYRawiCY3z5dYEDC8YIKH1VH/aLM1mdM4jLL5Ll520Ds2YU n9fOrKlskuJiydSOHYQmeFD9Ttej63dCJIj4wrgLIjdf8SuoJwBdG5PL/ g==; X-IronPort-AV: E=McAfee;i="6600,9927,10848"; a="3925487" X-IronPort-AV: E=Sophos;i="6.03,188,1694761200"; d="scan'208";a="3925487" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Sep 2023 11:14:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10848"; a="865777270" X-IronPort-AV: E=Sophos;i="6.03,188,1694761200"; d="scan'208";a="865777270" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga002.fm.intel.com with ESMTP; 29 Sep 2023 11:14:00 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 03/11] test/bbdev: rename macros from acc200 to vrb Date: Fri, 29 Sep 2023 11:13:20 -0700 Message-Id: <20230929181328.104311-4-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20230929181328.104311-1-hernan.vargas@intel.com> References: <20230929181328.104311-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Renaming ACC200 macros to use generic intel vRAN Boost (VRB). No functional impact. Signed-off-by: Hernan Vargas --- app/test-bbdev/test_bbdev_perf.c | 91 ++++++++++++++++---------------- 1 file changed, 45 insertions(+), 46 deletions(-) diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c index faea26c10eed..d4c001de0093 100644 --- a/app/test-bbdev/test_bbdev_perf.c +++ b/app/test-bbdev/test_bbdev_perf.c @@ -64,14 +64,14 @@ #define ACC100_QMGR_INVALID_IDX -1 #define ACC100_QMGR_RR 1 #define ACC100_QOS_GBR 0 -#define ACC200PF_DRIVER_NAME ("intel_acc200_pf") -#define ACC200VF_DRIVER_NAME ("intel_acc200_vf") -#define ACC200_QMGR_NUM_AQS 16 -#define ACC200_QMGR_NUM_QGS 2 -#define ACC200_QMGR_AQ_DEPTH 5 -#define ACC200_QMGR_INVALID_IDX -1 -#define ACC200_QMGR_RR 1 -#define ACC200_QOS_GBR 0 +#define VRBPF_DRIVER_NAME ("intel_vran_boost_pf") +#define VRBVF_DRIVER_NAME ("intel_vran_boost_vf") +#define VRB_QMGR_NUM_AQS 16 +#define VRB_QMGR_NUM_QGS 2 +#define VRB_QMGR_AQ_DEPTH 5 +#define VRB_QMGR_INVALID_IDX -1 +#define VRB_QMGR_RR 1 +#define VRB_QOS_GBR 0 #endif #define OPS_CACHE_SIZE 256U @@ -794,11 +794,11 @@ add_bbdev_dev(uint8_t dev_id, struct rte_bbdev_info *info, info->dev_name); } if ((get_init_device() == true) && - (!strcmp(info->drv.driver_name, ACC200PF_DRIVER_NAME))) { + (!strcmp(info->drv.driver_name, VRBPF_DRIVER_NAME))) { struct rte_acc_conf conf; unsigned int i; - printf("Configure ACC200 FEC Driver %s with default values\n", + printf("Configure Driver %s with default values\n", info->drv.driver_name); /* clear default configuration before initialization */ @@ -807,52 +807,51 @@ add_bbdev_dev(uint8_t dev_id, struct rte_bbdev_info *info, /* Always set in PF mode for built-in configuration */ conf.pf_mode_en = true; for (i = 0; i < RTE_ACC_NUM_VFS; ++i) { - conf.arb_dl_4g[i].gbr_threshold1 = ACC200_QOS_GBR; - conf.arb_dl_4g[i].gbr_threshold1 = ACC200_QOS_GBR; - conf.arb_dl_4g[i].round_robin_weight = ACC200_QMGR_RR; - conf.arb_ul_4g[i].gbr_threshold1 = ACC200_QOS_GBR; - conf.arb_ul_4g[i].gbr_threshold1 = ACC200_QOS_GBR; - conf.arb_ul_4g[i].round_robin_weight = ACC200_QMGR_RR; - conf.arb_dl_5g[i].gbr_threshold1 = ACC200_QOS_GBR; - conf.arb_dl_5g[i].gbr_threshold1 = ACC200_QOS_GBR; - conf.arb_dl_5g[i].round_robin_weight = ACC200_QMGR_RR; - conf.arb_ul_5g[i].gbr_threshold1 = ACC200_QOS_GBR; - conf.arb_ul_5g[i].gbr_threshold1 = ACC200_QOS_GBR; - conf.arb_ul_5g[i].round_robin_weight = ACC200_QMGR_RR; - conf.arb_fft[i].gbr_threshold1 = ACC200_QOS_GBR; - conf.arb_fft[i].gbr_threshold1 = ACC200_QOS_GBR; - conf.arb_fft[i].round_robin_weight = ACC200_QMGR_RR; + conf.arb_dl_4g[i].gbr_threshold1 = VRB_QOS_GBR; + conf.arb_dl_4g[i].gbr_threshold1 = VRB_QOS_GBR; + conf.arb_dl_4g[i].round_robin_weight = VRB_QMGR_RR; + conf.arb_ul_4g[i].gbr_threshold1 = VRB_QOS_GBR; + conf.arb_ul_4g[i].gbr_threshold1 = VRB_QOS_GBR; + conf.arb_ul_4g[i].round_robin_weight = VRB_QMGR_RR; + conf.arb_dl_5g[i].gbr_threshold1 = VRB_QOS_GBR; + conf.arb_dl_5g[i].gbr_threshold1 = VRB_QOS_GBR; + conf.arb_dl_5g[i].round_robin_weight = VRB_QMGR_RR; + conf.arb_ul_5g[i].gbr_threshold1 = VRB_QOS_GBR; + conf.arb_ul_5g[i].gbr_threshold1 = VRB_QOS_GBR; + conf.arb_ul_5g[i].round_robin_weight = VRB_QMGR_RR; + conf.arb_fft[i].gbr_threshold1 = VRB_QOS_GBR; + conf.arb_fft[i].gbr_threshold1 = VRB_QOS_GBR; + conf.arb_fft[i].round_robin_weight = VRB_QMGR_RR; } conf.input_pos_llr_1_bit = true; conf.output_pos_llr_1_bit = true; conf.num_vf_bundles = 1; /**< Number of VF bundles to setup */ - conf.q_ul_4g.num_qgroups = ACC200_QMGR_NUM_QGS; - conf.q_ul_4g.first_qgroup_index = ACC200_QMGR_INVALID_IDX; - conf.q_ul_4g.num_aqs_per_groups = ACC200_QMGR_NUM_AQS; - conf.q_ul_4g.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH; - conf.q_dl_4g.num_qgroups = ACC200_QMGR_NUM_QGS; - conf.q_dl_4g.first_qgroup_index = ACC200_QMGR_INVALID_IDX; - conf.q_dl_4g.num_aqs_per_groups = ACC200_QMGR_NUM_AQS; - conf.q_dl_4g.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH; - conf.q_ul_5g.num_qgroups = ACC200_QMGR_NUM_QGS; - conf.q_ul_5g.first_qgroup_index = ACC200_QMGR_INVALID_IDX; - conf.q_ul_5g.num_aqs_per_groups = ACC200_QMGR_NUM_AQS; - conf.q_ul_5g.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH; - conf.q_dl_5g.num_qgroups = ACC200_QMGR_NUM_QGS; - conf.q_dl_5g.first_qgroup_index = ACC200_QMGR_INVALID_IDX; - conf.q_dl_5g.num_aqs_per_groups = ACC200_QMGR_NUM_AQS; - conf.q_dl_5g.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH; - conf.q_fft.num_qgroups = ACC200_QMGR_NUM_QGS; - conf.q_fft.first_qgroup_index = ACC200_QMGR_INVALID_IDX; - conf.q_fft.num_aqs_per_groups = ACC200_QMGR_NUM_AQS; - conf.q_fft.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH; + conf.q_ul_4g.num_qgroups = VRB_QMGR_NUM_QGS; + conf.q_ul_4g.first_qgroup_index = VRB_QMGR_INVALID_IDX; + conf.q_ul_4g.num_aqs_per_groups = VRB_QMGR_NUM_AQS; + conf.q_ul_4g.aq_depth_log2 = VRB_QMGR_AQ_DEPTH; + conf.q_dl_4g.num_qgroups = VRB_QMGR_NUM_QGS; + conf.q_dl_4g.first_qgroup_index = VRB_QMGR_INVALID_IDX; + conf.q_dl_4g.num_aqs_per_groups = VRB_QMGR_NUM_AQS; + conf.q_dl_4g.aq_depth_log2 = VRB_QMGR_AQ_DEPTH; + conf.q_ul_5g.num_qgroups = VRB_QMGR_NUM_QGS; + conf.q_ul_5g.first_qgroup_index = VRB_QMGR_INVALID_IDX; + conf.q_ul_5g.num_aqs_per_groups = VRB_QMGR_NUM_AQS; + conf.q_ul_5g.aq_depth_log2 = VRB_QMGR_AQ_DEPTH; + conf.q_dl_5g.num_qgroups = VRB_QMGR_NUM_QGS; + conf.q_dl_5g.first_qgroup_index = VRB_QMGR_INVALID_IDX; + conf.q_dl_5g.num_aqs_per_groups = VRB_QMGR_NUM_AQS; + conf.q_dl_5g.aq_depth_log2 = VRB_QMGR_AQ_DEPTH; + conf.q_fft.num_qgroups = VRB_QMGR_NUM_QGS; + conf.q_fft.first_qgroup_index = VRB_QMGR_INVALID_IDX; + conf.q_fft.num_aqs_per_groups = VRB_QMGR_NUM_AQS; /* setup PF with configuration information */ ret = rte_acc_configure(info->dev_name, &conf); TEST_ASSERT_SUCCESS(ret, - "Failed to configure ACC200 PF for bbdev %s", + "Failed to configure PF for bbdev %s", info->dev_name); } #endif