From patchwork Tue Oct 10 17:54:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 132468 X-Patchwork-Delegate: maxime.coquelin@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E18A74234E; Tue, 10 Oct 2023 19:55:22 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6B008406FF; Tue, 10 Oct 2023 19:55:17 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id CCE34406FF for ; Tue, 10 Oct 2023 19:55:14 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1696960515; x=1728496515; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=C7XwnoeaTUX0e8v2vZjqeKx06STHttwJj2nweFi7ot0=; b=g0XpM/sX5KdVZhlSWZcyQvoIg2oTRusEsY2lbWqy/jEvQPP+D5zKomKM 9emaC876B64schwANzBvRM9yiUrnrqD/KoAwWCilGNLPEPnz3EWRw3+Di GGfd6ZDmNngJVyskabm2Ag+lwN4Wuqi5cPRYbPgu1VW+/aY1IusP0+3bA C7EIA9oVf5eV5fO3Uc7sj8YGWEETrG8H1yP8QNA4Qftr8XL5unq0Uw/pw hXrPEc1bvUJ4X7JGzS+1RnSt4nUqprFuxORqAlaUFUJ1rkbVRzEPtyM1E Kbj8HIxrbybHLGZoM5p4cO8SouLbJmIbwU7gr83HjVghMSHC4w2/GJSTj Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10859"; a="415497127" X-IronPort-AV: E=Sophos;i="6.03,213,1694761200"; d="scan'208";a="415497127" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2023 10:55:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10859"; a="1084896402" X-IronPort-AV: E=Sophos;i="6.03,213,1694761200"; d="scan'208";a="1084896402" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga005.fm.intel.com with ESMTP; 10 Oct 2023 10:55:00 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 1/2] baseband/acc: support ACC100 deRM corner case SDK Date: Tue, 10 Oct 2023 10:54:33 -0700 Message-Id: <20231010175434.249697-2-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20231010175434.249697-1-hernan.vargas@intel.com> References: <20231010175434.249697-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Implement de-ratematch pre-processing for ACC100 SW corner cases. Some specific 5GUL FEC corner cases may cause unintended back pressure and in some cases a potential stability issue on the ACC100. The PMD can detect such code block configuration and issue an info message to the user. Signed-off-by: Hernan Vargas --- drivers/baseband/acc/meson.build | 23 ++++++++++- drivers/baseband/acc/rte_acc100_pmd.c | 59 +++++++++++++++++++++++++-- 2 files changed, 77 insertions(+), 5 deletions(-) diff --git a/drivers/baseband/acc/meson.build b/drivers/baseband/acc/meson.build index 27a654b50153..84f4fea635ef 100644 --- a/drivers/baseband/acc/meson.build +++ b/drivers/baseband/acc/meson.build @@ -1,7 +1,28 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2020 Intel Corporation -deps += ['bus_pci'] +# check for FlexRAN SDK libraries +dep_dec5g = dependency('flexran_sdk_ldpc_decoder_5gnr', required: false) + +if dep_dec5g.found() + ext_deps += cc.find_library('stdc++', required: true) + ext_deps += cc.find_library('irc', required: true) + ext_deps += cc.find_library('imf', required: true) + ext_deps += cc.find_library('ipps', required: true) + ext_deps += cc.find_library('svml', required: true) + ext_deps += dep_dec5g + ext_deps += dependency('flexran_sdk_ldpc_encoder_5gnr', required: true) + ext_deps += dependency('flexran_sdk_LDPC_ratematch_5gnr', required: true) + ext_deps += dependency('flexran_sdk_rate_dematching_5gnr', required: true) + ext_deps += dependency('flexran_sdk_turbo', required: true) + ext_deps += dependency('flexran_sdk_crc', required: true) + ext_deps += dependency('flexran_sdk_rate_matching', required: true) + ext_deps += dependency('flexran_sdk_common', required: true) + cflags += ['-DRTE_BBDEV_SDK_AVX2'] + cflags += ['-DRTE_BBDEV_SDK_AVX512'] +endif + +deps += ['bbdev', 'bus_pci'] sources = files('rte_acc100_pmd.c', 'rte_vrb_pmd.c') diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 5362d39c302f..e45137212f68 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -22,6 +22,10 @@ #include "acc101_pmd.h" #include "vrb_cfg.h" +#ifdef RTE_BBDEV_SDK_AVX512 +#include +#endif + #ifdef RTE_LIBRTE_BBDEV_DEBUG RTE_LOG_REGISTER_DEFAULT(acc100_logtype, DEBUG); #else @@ -3058,7 +3062,8 @@ derm_workaround_recommended(struct rte_bbdev_op_ldpc_dec *ldpc_dec, struct acc_q /** Enqueue one decode operations for ACC100 device in CB mode */ static inline int enqueue_ldpc_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op, - uint16_t total_enqueued_cbs, bool same_op) + uint16_t total_enqueued_cbs, bool same_op, + struct rte_bbdev_queue_data *q_data) { int ret; if (unlikely(check_bit(op->ldpc_dec.op_flags, @@ -3113,8 +3118,54 @@ enqueue_ldpc_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw; uint32_t seg_total_left; - if (derm_workaround_recommended(&op->ldpc_dec, q)) - rte_bbdev_log(INFO, "Corner case may require deRM pre-processing"); + if (derm_workaround_recommended(&op->ldpc_dec, q)) { + #ifdef RTE_BBDEV_SDK_AVX512 + struct rte_bbdev_op_ldpc_dec *dec = &op->ldpc_dec; + struct bblib_rate_dematching_5gnr_request derm_req; + struct bblib_rate_dematching_5gnr_response derm_resp; + uint8_t *in; + + /* Checking input size is matching with E */ + if (dec->input.data->data_len < (dec->cb_params.e % 65536)) { + rte_bbdev_log(ERR, "deRM: Input size mismatch"); + return -EFAULT; + } + /* Run first deRM processing in SW */ + in = rte_pktmbuf_mtod_offset(dec->input.data, uint8_t *, in_offset); + derm_req.p_in = (int8_t *) in; + derm_req.p_harq = (int8_t *) q->derm_buffer; + derm_req.base_graph = dec->basegraph; + derm_req.zc = dec->z_c; + derm_req.ncb = dec->n_cb; + derm_req.e = dec->cb_params.e; + if (derm_req.e > ACC_MAX_E) { + rte_bbdev_log(WARNING, + "deRM: E %d > %d max", + derm_req.e, ACC_MAX_E); + derm_req.e = ACC_MAX_E; + } + derm_req.k0 = 0; /* Actual output from SDK */ + derm_req.isretx = false; + derm_req.rvid = dec->rv_index; + derm_req.modulation_order = dec->q_m; + derm_req.start_null_index = + (dec->basegraph == 1 ? 22 : 10) + * dec->z_c - 2 * dec->z_c + - dec->n_filler; + derm_req.num_of_null = dec->n_filler; + bblib_rate_dematching_5gnr(&derm_req, &derm_resp); + /* Force back the HW DeRM */ + dec->q_m = 1; + dec->cb_params.e = dec->n_cb - dec->n_filler; + dec->rv_index = 0; + rte_memcpy(in, q->derm_buffer, dec->cb_params.e); + /* Capture counter when pre-processing is used */ + q_data->queue_stats.enqueue_warn_count++; + #else + RTE_SET_USED(q_data); + rte_bbdev_log(INFO, "Corner case may require deRM pre-processing in SDK"); + #endif + } fcw = &desc->req.fcw_ld; q->d->fcw_ld_fill(op, fcw, harq_layout); @@ -3647,7 +3698,7 @@ acc100_enqueue_ldpc_dec_cb(struct rte_bbdev_queue_data *q_data, ops[i]->ldpc_dec.n_cb, ops[i]->ldpc_dec.q_m, ops[i]->ldpc_dec.n_filler, ops[i]->ldpc_dec.cb_params.e, same_op); - ret = enqueue_ldpc_dec_one_op_cb(q, ops[i], i, same_op); + ret = enqueue_ldpc_dec_one_op_cb(q, ops[i], i, same_op, q_data); if (ret < 0) { acc_enqueue_invalid(q_data); break;