From patchwork Wed Oct 11 01:50:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vamsi Krishna Attunuru X-Patchwork-Id: 132488 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 720C342358; Wed, 11 Oct 2023 03:51:17 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 52B55402DA; Wed, 11 Oct 2023 03:51:13 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 36532400EF for ; Wed, 11 Oct 2023 03:51:11 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39AIbe4R020001 for ; Tue, 10 Oct 2023 18:51:10 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=VEvjjFs5jVw++n8MJB8t7s72HGlp5/ALeYTSOQ7d2oY=; b=NXl45v5X1IZ99LamQbf7pp3fdMFCFSr15XReR1CJDSCbZfYQGRm2KMAmUI3gMU1XVHgP 6JQj2ueCF3ajfUrEtVfsUiQbhRgqi6IlCqPIfEEeQ04H5bSGyxEpb6f4NFjMGuyd5ta6 NroerJ2oO3z+Kz+giHqO86mSMDXhcpotxTvcjfykIkIJSxP2EhzAd30re7dazfnMdeCI FAjcuQI4uV0efg72MhlwdzNkLIcZnEHWxv2Kf9KKLoM2Th7+9xud/VQvo2WVNGeSbUZQ mIQzSoF6FgfUIBBkY3Mtu5mGGgqQsqhmeQRZYpASsjjy37qnKkfhzoUxl4iYrIuKxUvv XQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3tnc2as6xy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 10 Oct 2023 18:51:10 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 10 Oct 2023 18:51:09 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 10 Oct 2023 18:51:08 -0700 Received: from localhost.localdomain (unknown [10.28.36.156]) by maili.marvell.com (Postfix) with ESMTP id 628365B6934; Tue, 10 Oct 2023 18:51:07 -0700 (PDT) From: Vamsi Attunuru To: , CC: Subject: [PATCH 1/3] net/octeon_ep: support 32B IQ descriptor size Date: Tue, 10 Oct 2023 18:50:52 -0700 Message-ID: <20231011015054.524907-2-vattunuru@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231011015054.524907-1-vattunuru@marvell.com> References: <20231011015054.524907-1-vattunuru@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 2eAH8QoZ_QOSVHAlPDbhDqWx54mlPY1Y X-Proofpoint-ORIG-GUID: 2eAH8QoZ_QOSVHAlPDbhDqWx54mlPY1Y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-10_19,2023-10-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shijith Thotton Update input queue setup to consider descriptor size in driver conf. The default instruction size for otx2 and cnxk devices has been updated to 32 bytes. Signed-off-by: Shijith Thotton --- drivers/net/octeon_ep/cnxk_ep_vf.c | 10 +++++++++- drivers/net/octeon_ep/otx2_ep_vf.c | 10 +++++++++- drivers/net/octeon_ep/otx_ep_common.h | 4 ++++ drivers/net/octeon_ep/otx_ep_rxtx.c | 8 +++----- drivers/net/octeon_ep/otx_ep_vf.c | 8 ++++++++ 5 files changed, 33 insertions(+), 7 deletions(-) diff --git a/drivers/net/octeon_ep/cnxk_ep_vf.c b/drivers/net/octeon_ep/cnxk_ep_vf.c index 92c2d2ca5c..7b3669fe0c 100644 --- a/drivers/net/octeon_ep/cnxk_ep_vf.c +++ b/drivers/net/octeon_ep/cnxk_ep_vf.c @@ -106,6 +106,14 @@ cnxk_ep_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no) return -EIO; } + /* Configure input queue instruction size. */ + if (otx_ep->conf->iq.instr_type == OTX_EP_32BYTE_INSTR) + reg_val &= ~(CNXK_EP_R_IN_CTL_IS_64B); + else + reg_val |= CNXK_EP_R_IN_CTL_IS_64B; + oct_ep_write64(reg_val, otx_ep->hw_addr + CNXK_EP_R_IN_CONTROL(iq_no)); + iq->desc_size = otx_ep->conf->iq.instr_type; + /* Write the start of the input queue's ring and its size */ oct_ep_write64(iq->base_addr_dma, otx_ep->hw_addr + CNXK_EP_R_IN_INSTR_BADDR(iq_no)); oct_ep_write64(iq->nb_desc, otx_ep->hw_addr + CNXK_EP_R_IN_INSTR_RSIZE(iq_no)); @@ -354,7 +362,7 @@ static const struct otx_ep_config default_cnxk_ep_conf = { /* IQ attributes */ .iq = { .max_iqs = OTX_EP_CFG_IO_QUEUES, - .instr_type = OTX_EP_64BYTE_INSTR, + .instr_type = OTX_EP_32BYTE_INSTR, .pending_list_size = (OTX_EP_MAX_IQ_DESCRIPTORS * OTX_EP_CFG_IO_QUEUES), }, diff --git a/drivers/net/octeon_ep/otx2_ep_vf.c b/drivers/net/octeon_ep/otx2_ep_vf.c index ced3a415a5..f72b8d25d7 100644 --- a/drivers/net/octeon_ep/otx2_ep_vf.c +++ b/drivers/net/octeon_ep/otx2_ep_vf.c @@ -256,6 +256,14 @@ otx2_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no) return -EIO; } + /* Configure input queue instruction size. */ + if (otx_ep->conf->iq.instr_type == OTX_EP_32BYTE_INSTR) + reg_val &= ~(SDP_VF_R_IN_CTL_IS_64B); + else + reg_val |= SDP_VF_R_IN_CTL_IS_64B; + oct_ep_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_IN_CONTROL(iq_no)); + iq->desc_size = otx_ep->conf->iq.instr_type; + /* Write the start of the input queue's ring and its size */ oct_ep_write64(iq->base_addr_dma, otx_ep->hw_addr + SDP_VF_R_IN_INSTR_BADDR(iq_no)); oct_ep_write64(iq->nb_desc, otx_ep->hw_addr + SDP_VF_R_IN_INSTR_RSIZE(iq_no)); @@ -500,7 +508,7 @@ static const struct otx_ep_config default_otx2_ep_conf = { /* IQ attributes */ .iq = { .max_iqs = OTX_EP_CFG_IO_QUEUES, - .instr_type = OTX_EP_64BYTE_INSTR, + .instr_type = OTX_EP_32BYTE_INSTR, .pending_list_size = (OTX_EP_MAX_IQ_DESCRIPTORS * OTX_EP_CFG_IO_QUEUES), }, diff --git a/drivers/net/octeon_ep/otx_ep_common.h b/drivers/net/octeon_ep/otx_ep_common.h index c150cbe619..90e059cad0 100644 --- a/drivers/net/octeon_ep/otx_ep_common.h +++ b/drivers/net/octeon_ep/otx_ep_common.h @@ -11,6 +11,7 @@ #define OTX_EP_MAX_RINGS_PER_VF (8) #define OTX_EP_CFG_IO_QUEUES OTX_EP_MAX_RINGS_PER_VF +#define OTX_EP_32BYTE_INSTR (32) #define OTX_EP_64BYTE_INSTR (64) /* * Backpressure for SDP is configured on Octeon, and the minimum queue sizes @@ -215,6 +216,9 @@ struct otx_ep_instr_queue { /* Number of descriptors in this ring. */ uint32_t nb_desc; + /* Size of the descriptor. */ + uint8_t desc_size; + /* Input ring index, where the driver should write the next packet */ uint32_t host_write_index; diff --git a/drivers/net/octeon_ep/otx_ep_rxtx.c b/drivers/net/octeon_ep/otx_ep_rxtx.c index b37fc8109f..5b759d759b 100644 --- a/drivers/net/octeon_ep/otx_ep_rxtx.c +++ b/drivers/net/octeon_ep/otx_ep_rxtx.c @@ -484,7 +484,7 @@ otx_ep_ring_doorbell(struct otx_ep_device *otx_ep __rte_unused, static inline int post_iqcmd(struct otx_ep_instr_queue *iq, uint8_t *iqcmd) { - uint8_t *iqptr, cmdsize; + uint8_t *iqptr; /* This ensures that the read index does not wrap around to * the same position if queue gets full before OCTEON 9 could @@ -494,10 +494,8 @@ post_iqcmd(struct otx_ep_instr_queue *iq, uint8_t *iqcmd) return OTX_EP_IQ_SEND_FAILED; /* Copy cmd into iq */ - cmdsize = 64; - iqptr = iq->base_addr + (iq->host_write_index << 6); - - rte_memcpy(iqptr, iqcmd, cmdsize); + iqptr = iq->base_addr + (iq->host_write_index * iq->desc_size); + rte_memcpy(iqptr, iqcmd, iq->desc_size); /* Increment the host write index */ iq->host_write_index = diff --git a/drivers/net/octeon_ep/otx_ep_vf.c b/drivers/net/octeon_ep/otx_ep_vf.c index 4f3538146b..236b7a874c 100644 --- a/drivers/net/octeon_ep/otx_ep_vf.c +++ b/drivers/net/octeon_ep/otx_ep_vf.c @@ -120,6 +120,14 @@ otx_ep_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no) return -EIO; } + /* Configure input queue instruction size. */ + if (iq->desc_size == OTX_EP_32BYTE_INSTR) + reg_val &= ~(OTX_EP_R_IN_CTL_IS_64B); + else + reg_val |= OTX_EP_R_IN_CTL_IS_64B; + oct_ep_write64(reg_val, otx_ep->hw_addr + OTX_EP_R_IN_CONTROL(iq_no)); + iq->desc_size = otx_ep->conf->iq.instr_type; + /* Write the start of the input queue's ring and its size */ otx_ep_write64(iq->base_addr_dma, otx_ep->hw_addr, OTX_EP_R_IN_INSTR_BADDR(iq_no));