From patchwork Thu Oct 26 16:38:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sevincer, Abdullah" X-Patchwork-Id: 133434 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 027EB4320A; Thu, 26 Oct 2023 18:39:31 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 80DC740A80; Thu, 26 Oct 2023 18:39:31 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id A330840A6D for ; Thu, 26 Oct 2023 18:39:29 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698338370; x=1729874370; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ygv0WmGmqgRgFYL81FhYlTz5ZakkNVhnKbUAbN3MMbA=; b=feH7pakWljpZh+e5MXNaMQF9ZJfCA2IAs3Oj/REbqkvRXloP+eO3WxL0 W7zJo6rURse/+ZjGEZgaKrXggbu/LBnADkOL/HKiemkeUO9avWhKdVtn4 aKC1ETuDgY5fokqa2qyB8XHz77zjSM1dFZwdOiIR7brVMNlpwHLvfwZnv 6IfJ9Wo+ciR3liTMRV7DViofuUR7OgHjnZEXuToy9spY+L1LZyLSTD7H7 Z3vvFFGBgdd/nv+Qubw3Un9QVuMkAngjld6sx7hrp43IrtrXssBrp5m8J rEPVFHOR7/MmtIzTr2at95IMkK3nNIgUpot8CQegWe1au1VLahck8HmHD g==; X-IronPort-AV: E=McAfee;i="6600,9927,10875"; a="451829297" X-IronPort-AV: E=Sophos;i="6.03,254,1694761200"; d="scan'208";a="451829297" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Oct 2023 09:38:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10875"; a="1006446415" X-IronPort-AV: E=Sophos;i="6.03,254,1694761200"; d="scan'208";a="1006446415" Received: from txanpdk02.an.intel.com ([10.123.117.76]) by fmsmga006.fm.intel.com with ESMTP; 26 Oct 2023 09:38:06 -0700 From: Abdullah Sevincer To: dev@dpdk.org Cc: jerinj@marvell.com, mike.ximing.chen@intel.com, bruce.richardson@intel.com, Abdullah Sevincer Subject: [PATCH v2] event/dlb2: disable PASID for kernel 6.2 Date: Thu, 26 Oct 2023 11:38:02 -0500 Message-Id: <20231026163802.2247563-1-abdullah.sevincer@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230607210050.107944-1-abdullah.sevincer@intel.com> References: <20230607210050.107944-1-abdullah.sevincer@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org vfio-pci driver in Linux kernel 6.2 enables PASID by default. In DLB hardware, enabling PASID puts DLB in SIOV mode. This breaks DLB PF-PMD mode. For DLB PF-PMD mode to function properly PASID needs to be disabled for kernel 6.2. In this commit this issue is addressed and PASID is disabled by writing a zero to PASID control register. Signed-off-by: Abdullah Sevincer --- drivers/event/dlb2/pf/dlb2_main.c | 24 ++++++++++++++++++++++++ lib/pci/rte_pci.h | 4 ++++ 2 files changed, 28 insertions(+) diff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c index aa03e4c311..5065c0a9e4 100644 --- a/drivers/event/dlb2/pf/dlb2_main.c +++ b/drivers/event/dlb2/pf/dlb2_main.c @@ -190,6 +190,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) uint16_t rt_ctl_word; uint32_t pri_reqs_dword; uint16_t pri_ctrl_word; + uint16_t pasid_ctrl; off_t pcie_cap_offset; int pri_cap_offset; @@ -197,6 +198,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) int err_cap_offset; int acs_cap_offset; int wait_count; + int pasid_cap_offset; uint16_t devsta_busy_word; uint16_t devctl_word; @@ -514,6 +516,28 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) } } + pasid_cap_offset = rte_pci_find_ext_capability(pdev, RTE_PCI_EXT_CAP_ID_PASID); + + if (pasid_cap_offset >= 0) { + off = pasid_cap_offset + RTE_PCI_PASID_CTRL; + + if (rte_pci_read_config(pdev, &pasid_ctrl, 2, off) != 2) + pasid_ctrl = 0; + + if (pasid_ctrl) { + + DLB2_INFO(dlb2_dev, "DLB2 disabling pasid...\n"); + pasid_ctrl = 0; + ret = rte_pci_write_config(pdev, &pasid_ctrl, 2, off); + + if (ret != 2) { + DLB2_LOG_ERR("[%s()] failed to write the pcie config space at offset %d\n", + __func__, (int)off); + return ret; + } + } + } + return 0; } diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h index 69e932d910..d195f01950 100644 --- a/lib/pci/rte_pci.h +++ b/lib/pci/rte_pci.h @@ -101,6 +101,10 @@ extern "C" { #define RTE_PCI_EXT_CAP_ID_ACS 0x0d /* Access Control Services */ #define RTE_PCI_EXT_CAP_ID_SRIOV 0x10 /* SR-IOV */ #define RTE_PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ +#define RTE_PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ + +/* Process Address Space ID */ +#define RTE_PCI_PASID_CTRL 0x06 /* PASID control register */ /* Advanced Error Reporting (RTE_PCI_EXT_CAP_ID_ERR) */ #define RTE_PCI_ERR_UNCOR_STATUS 0x04 /* Uncorrectable Error Status */