From patchwork Sun Oct 29 16:31:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory Etelson X-Patchwork-Id: 133595 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D0FFD43238; Sun, 29 Oct 2023 17:35:45 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 980A540E96; Sun, 29 Oct 2023 17:33:43 +0100 (CET) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2048.outbound.protection.outlook.com [40.107.94.48]) by mails.dpdk.org (Postfix) with ESMTP id 061D842DCB for ; Sun, 29 Oct 2023 17:33:42 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=WWLiEj4VsGH4LZ9kQ+OK3AoVgtjKAmoKkTIaUMiky6wbMsIYfcUhUwDBUkjyI5dceVb68CdqWCzvAyXXtX5TpSGi8e2kyA1WhNkh8QB2DfjWcdAjcNBed0u0ilPiYusQw7naxV7W4SaKlnPkzMbp2+sP1HHYn/ujAfsN4UHdXwWtM396HFBPL7r2mhe+KllS+eLMQ/Mo55XkI//1d1GDP4EsEW5ydfghy5RS0shmwCoKLgneb8XmNPnzef69LHAfmUwXD3pBMIZSCkbWmgoCVVEdc7txjTToQD4KMwDsvk5PP5axAeUmhIjiIJ7leJ0KEA5oZGl7kO805GDLrIErvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=D0FH8a9CyviaqAyWMFP8igj/NO06p9+bY7HeX9M6+QQ=; b=F+GvKxmpoXP2hlP29CEQD+p1WH4UP7v6MCtroxzsokuTJHNvl5dZULmy+nnVz87zgy3181d6IjrHtOUbkPCaVXbQHblSovczXgSD7fqe12pTh7hZJvlIwbholItfau2b1Ysgphvz99P5l/qLr6dAn9V+94SMVeVGNYLehDfrovXZ5dvE8K2vjELMxbyvDVNkt3si6p9QFh5MW4tcWCNgwZIjOokLTGarGktHL68RoozfzJhNmEsMthDx0xW9qAgDnT3bwRqAunc4osTcQ+oFmihd+KFNa5c2RCmfxiXgwcdv1duDaWt2GpdkcefLciNBaN1V8tpUtQo5dN2Yx/UvLA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=D0FH8a9CyviaqAyWMFP8igj/NO06p9+bY7HeX9M6+QQ=; b=kzSxn0Y6V3+Rxkd8uHs53h9DqDk+RXkkC8LGhl4Qin2MmL60xLF1/0T2C5Z9Q3KqYy4hiN9B/9ki/l/4Uk1aKJYNhUEG4g9vevmtgYgcw8CE8v3TaYegRJhE5ynu1lizW96L33vDreu66ns2BhVZA1UgRaZqG2khdjwybpxrvF/xb+yBzQ0UZTyfk9707WAu1rGdZkgCtNomlicAGhEyjudEa3TsB1hsaWIB13dn0NIdSFxlTOZzgvRatnVhb1yn1oVVwGsiPzBIGvwbh+GBssTvrzTLaEe7KIyoCgEMHj+ZRrdrobH7Ucm58+cHgnzF9Qf7nYQeK35hIqfKaeBRDw== Received: from BL1PR13CA0104.namprd13.prod.outlook.com (2603:10b6:208:2b9::19) by IA0PR12MB7627.namprd12.prod.outlook.com (2603:10b6:208:437::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6933.27; Sun, 29 Oct 2023 16:33:39 +0000 Received: from BL02EPF0001A100.namprd03.prod.outlook.com (2603:10b6:208:2b9:cafe::b7) by BL1PR13CA0104.outlook.office365.com (2603:10b6:208:2b9::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6954.15 via Frontend Transport; Sun, 29 Oct 2023 16:33:39 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BL02EPF0001A100.mail.protection.outlook.com (10.167.242.107) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6933.15 via Frontend Transport; Sun, 29 Oct 2023 16:33:39 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Sun, 29 Oct 2023 09:33:28 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Sun, 29 Oct 2023 09:33:25 -0700 From: Gregory Etelson To: CC: , , , "Alex Vesker" , Erez Shitrit , Matan Azrad , Viacheslav Ovsiienko , Ori Kam , Suanming Mou Subject: [PATCH 22/30] net/mlx5/hws: allow jump to TIR over FDB Date: Sun, 29 Oct 2023 18:31:54 +0200 Message-ID: <20231029163202.216450-22-getelson@nvidia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231029163202.216450-1-getelson@nvidia.com> References: <20231029163202.216450-1-getelson@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A100:EE_|IA0PR12MB7627:EE_ X-MS-Office365-Filtering-Correlation-Id: 41a0a8b5-df7e-4ea5-8831-08dbd89cced5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: h5ai6X8h6WHFrJVrjHWAfV3vk21Qvv9qPDyySjXTXnfdc2e2Fd/V2Ko/CArJBKSGYAJPoblcJjNHWtY3g6Pp/FxMopKw/rQPBZUIjCSI+yPERnIt0kzwGpcXWmMBdIw0Zz8MFRq+J3r6ClzYX5kTR+c1+O/rDRaCvcruLU3rhE9SfVT/Ki3ZRhke/Pg1dxy9+OYUqP8sbioajapVr7AgE9j+gRQAyRavcki+6+tk5x9CNQZfUu0ORnE2TBYsqChhVaUiBS/CSQCi5N+XONHMH4XhRy44pxmH0OoXQEFPpet2dcyBtn0+ajUmst99dAZdtpUaHLzU2cJU6K88B4Qb7YTNBPPctmJR8rx2CbR1wFcGOBGQG5VRN6d+DvkGv1qcJ2CZAsOsCKHLeDrFq2yShJR75tX5PQzlt3DBRB7y83vo4gu7yUeGB668OMDHQCTJDXkXYfMKgQz7TgfJuTTcRScBAe52f/dLnFJmVNLwjZX+IiVX4p8nrIhZay8Zoqb2XcVKap/L/lS5gzgFwaY7bvsppoYF9qJBI+rqa6m+H081bQfeimE6PM+7gycnHyDdyw/bHYqx4pHKw6utrvkdYR2RSqZ4FyyId20MaX4d5gt14IXtteWVEagVIioTeP36hgyUxeleRuetqbXI/VdJJ0MuMAX8oFvGmFlsPA90GiIHIEO/7jPuA70L9RZV4e5lB91B7iAwLGsg2DK7CqixL3kGLsRBAxTKz3LddUiTZ1M4jurNtBpQB0Odpo3yKgwA X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230031)(4636009)(396003)(346002)(39860400002)(376002)(136003)(230922051799003)(451199024)(64100799003)(186009)(1800799009)(82310400011)(40470700004)(46966006)(36840700001)(55016003)(40460700003)(2906002)(36860700001)(6916009)(54906003)(70586007)(70206006)(47076005)(356005)(7636003)(82740400003)(316002)(6666004)(7696005)(478600001)(83380400001)(2616005)(107886003)(336012)(426003)(16526019)(6286002)(1076003)(26005)(41300700001)(5660300002)(8936002)(8676002)(4326008)(86362001)(40480700001)(36756003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2023 16:33:39.7624 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 41a0a8b5-df7e-4ea5-8831-08dbd89cced5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A100.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7627 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Alex Vesker Current TIR action is allowed to be used only for NIC RX, this will allow TIR action over FDB for RX traffic in case of TX traffic packets will be dropped. Signed-off-by: Alex Vesker Reviewed-by: Erez Shitrit Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_prm.h | 2 ++ drivers/net/mlx5/hws/mlx5dr_action.c | 27 ++++++++++++++++++++++----- drivers/net/mlx5/hws/mlx5dr_cmd.c | 4 ++++ drivers/net/mlx5/hws/mlx5dr_cmd.h | 1 + 4 files changed, 29 insertions(+), 5 deletions(-) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 40e461cb82..bb2b990d5b 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -2418,6 +2418,8 @@ struct mlx5_ifc_wqe_based_flow_table_cap_bits { u8 reserved_at_180[0x10]; u8 ste_format_gen_wqe[0x10]; u8 linear_match_definer_reg_c3[0x20]; + u8 fdb_jump_to_tir_stc[0x1]; + u8 reserved_at_1c1[0x1f]; }; union mlx5_ifc_hca_cap_union_bits { diff --git a/drivers/net/mlx5/hws/mlx5dr_action.c b/drivers/net/mlx5/hws/mlx5dr_action.c index 1a6296a728..05b6e97576 100644 --- a/drivers/net/mlx5/hws/mlx5dr_action.c +++ b/drivers/net/mlx5/hws/mlx5dr_action.c @@ -445,6 +445,7 @@ mlx5dr_action_fixup_stc_attr(struct mlx5dr_context *ctx, break; case MLX5_IFC_STC_ACTION_TYPE_CRYPTO_IPSEC_ENCRYPTION: + /* Encrypt is allowed on RX side, requires mask in case of FDB */ if (fw_tbl_type == FS_FT_FDB_RX) { fixup_stc_attr->action_type = MLX5_IFC_STC_ACTION_TYPE_NOP; fixup_stc_attr->action_offset = stc_attr->action_offset; @@ -454,6 +455,7 @@ mlx5dr_action_fixup_stc_attr(struct mlx5dr_context *ctx, break; case MLX5_IFC_STC_ACTION_TYPE_CRYPTO_IPSEC_DECRYPTION: + /* Decrypt is allowed on TX side, requires mask in case of FDB */ if (fw_tbl_type == FS_FT_FDB_TX) { fixup_stc_attr->action_type = MLX5_IFC_STC_ACTION_TYPE_NOP; fixup_stc_attr->action_offset = stc_attr->action_offset; @@ -463,12 +465,10 @@ mlx5dr_action_fixup_stc_attr(struct mlx5dr_context *ctx, break; case MLX5_IFC_STC_ACTION_TYPE_TRAILER: - if (table_type != MLX5DR_TABLE_TYPE_FDB) - break; - + /* Trailer has FDB limitations on RX and TX based on operation */ val = stc_attr->reformat_trailer.op; - if ((val == MLX5DR_ACTION_TRAILER_OP_INSERT && !is_mirror) || - (val == MLX5DR_ACTION_TRAILER_OP_REMOVE && is_mirror)) { + if ((val == MLX5DR_ACTION_TRAILER_OP_INSERT && fw_tbl_type == FS_FT_FDB_RX) || + (val == MLX5DR_ACTION_TRAILER_OP_REMOVE && fw_tbl_type == FS_FT_FDB_TX)) { fixup_stc_attr->action_type = MLX5_IFC_STC_ACTION_TYPE_NOP; fixup_stc_attr->action_offset = stc_attr->action_offset; fixup_stc_attr->stc_offset = stc_attr->stc_offset; @@ -476,6 +476,16 @@ mlx5dr_action_fixup_stc_attr(struct mlx5dr_context *ctx, } break; + case MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_TIR: + /* TIR is allowed on RX side, requires mask in case of FDB */ + if (fw_tbl_type == FS_FT_FDB_TX) { + fixup_stc_attr->action_type = MLX5_IFC_STC_ACTION_TYPE_DROP; + fixup_stc_attr->action_offset = MLX5DR_ACTION_OFFSET_HIT; + fixup_stc_attr->stc_offset = stc_attr->stc_offset; + use_fixup = true; + } + break; + default: break; } @@ -976,6 +986,13 @@ mlx5dr_action_create_dest_tir(struct mlx5dr_context *ctx, return NULL; } + if ((flags & MLX5DR_ACTION_FLAG_ROOT_FDB) || + (flags & MLX5DR_ACTION_FLAG_HWS_FDB && !ctx->caps->fdb_tir_stc)) { + DR_LOG(ERR, "TIR action not support on FDB"); + rte_errno = ENOTSUP; + return NULL; + } + if (!is_local) { DR_LOG(ERR, "TIR should be created on local ibv_device, flags: 0x%x", flags); diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c b/drivers/net/mlx5/hws/mlx5dr_cmd.c index 0ba4774f08..135d31dca1 100644 --- a/drivers/net/mlx5/hws/mlx5dr_cmd.c +++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c @@ -1275,6 +1275,10 @@ int mlx5dr_cmd_query_caps(struct ibv_context *ctx, caps->supp_ste_format_gen_wqe = MLX5_GET(query_hca_cap_out, out, capability.wqe_based_flow_table_cap. ste_format_gen_wqe); + + caps->fdb_tir_stc = MLX5_GET(query_hca_cap_out, out, + capability.wqe_based_flow_table_cap. + fdb_jump_to_tir_stc); } if (caps->eswitch_manager) { diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.h b/drivers/net/mlx5/hws/mlx5dr_cmd.h index c082157538..cb27212a5b 100644 --- a/drivers/net/mlx5/hws/mlx5dr_cmd.h +++ b/drivers/net/mlx5/hws/mlx5dr_cmd.h @@ -241,6 +241,7 @@ struct mlx5dr_cmd_query_caps { uint8_t log_header_modify_argument_granularity; uint8_t log_header_modify_argument_max_alloc; uint8_t sq_ts_format; + uint8_t fdb_tir_stc; uint64_t definer_format_sup; uint32_t trivial_match_definer; uint32_t vhca_id;