From patchwork Fri Nov 3 17:03:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abdullah Sevincer X-Patchwork-Id: 133847 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 308354327C; Fri, 3 Nov 2023 18:04:36 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1672440263; Fri, 3 Nov 2023 18:04:36 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 1EAF74014F for ; Fri, 3 Nov 2023 18:04:33 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699031074; x=1730567074; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=OIuEqHylrQa6a91LvQvTW5/YVRKRKmUZZO/B2fkLDT8=; b=M+86XGKGm12BvmDSJ2CtzhDMoldCU+6ktyIbvQXzk4kRzSWItAXaI5Bt E3Bm2Lj3vKNyTnH12NC7bNWck1tGtOYJP6v322i38AKaBhEHHmvgpZ3n5 eICxnZX6WcROH4XnfOSZwabbcw9/v6rlmJNserm921Q6gAR9FREw6zBR8 wgdkCfoazRIIledDGOhkrcXzsSKaJAR0QT/2SBnMWnUhP96Fj60ONN2ej VV4vXdB6L73fG0jzJ2AjpiMIqxxvj2td+ch8ahYFg9EA0J6xX4eg+KxBr Or2p3OXpPHkz9Pgxr2NGObY73O9waqITRL2koRjbjisnqLU+DBPOkHUxC A==; X-IronPort-AV: E=McAfee;i="6600,9927,10883"; a="391852860" X-IronPort-AV: E=Sophos;i="6.03,273,1694761200"; d="scan'208";a="391852860" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2023 10:03:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10883"; a="1093124212" X-IronPort-AV: E=Sophos;i="6.03,273,1694761200"; d="scan'208";a="1093124212" Received: from txanpdk02.an.intel.com ([10.123.117.76]) by fmsmga005.fm.intel.com with ESMTP; 03 Nov 2023 10:03:49 -0700 From: Abdullah Sevincer To: dev@dpdk.org Cc: jerinj@marvell.com, mike.ximing.chen@intel.com, bruce.richardson@intel.com, thomas@monjalon.net, Abdullah Sevincer Subject: [PATCH v1] bus/pci: add function to enable/disable PASID Date: Fri, 3 Nov 2023 12:03:47 -0500 Message-Id: <20231103170347.2790525-1-abdullah.sevincer@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This commit implements an internal api to enable and disable PASID for a device e.g. DLB Device. For kernels when PASID enabled by default it breaks DLB functionality, hence disabling PASID is required for DLB to function properly. PASID capability is not exposed to users hence offset can not be retrieved by rte_pci_find_ext_capability() api. Therefore, api implemented in this commit accepts an offset for PASID with an enable flag which is used to enable/disable PASID. Signed-off-by: Abdullah Sevincer --- drivers/bus/pci/pci_common.c | 7 +++++++ drivers/bus/pci/rte_bus_pci.h | 11 +++++++++++ drivers/bus/pci/version.map | 1 + lib/pci/rte_pci.h | 5 +++++ 4 files changed, 24 insertions(+) diff --git a/drivers/bus/pci/pci_common.c b/drivers/bus/pci/pci_common.c index 921d957bf6..ced072825e 100644 --- a/drivers/bus/pci/pci_common.c +++ b/drivers/bus/pci/pci_common.c @@ -938,6 +938,13 @@ rte_pci_set_bus_master(const struct rte_pci_device *dev, bool enable) return 0; } +int +rte_pci_set_pasid(const struct rte_pci_device *dev, off_t offset, bool enable) +{ + uint16_t pasid = enable; + return rte_pci_write_config(dev, &pasid, sizeof(pasid), offset) < 0 ? -1 : 0; +} + struct rte_pci_bus rte_pci_bus = { .bus = { .scan = rte_pci_scan, diff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h index 21e234abf0..d97c8320a7 100644 --- a/drivers/bus/pci/rte_bus_pci.h +++ b/drivers/bus/pci/rte_bus_pci.h @@ -295,6 +295,17 @@ void rte_pci_ioport_read(struct rte_pci_ioport *p, void rte_pci_ioport_write(struct rte_pci_ioport *p, const void *data, size_t len, off_t offset); +/** + * Enable/Disable PASID. + * + * @param offset + * Offset of the PASID external capability. + * @param enable + * Flag to enable or disable PASID. + */ +__rte_internal +int rte_pci_set_pasid(const struct rte_pci_device *dev, off_t offset, bool enable); + #ifdef __cplusplus } #endif diff --git a/drivers/bus/pci/version.map b/drivers/bus/pci/version.map index 74c5b075d5..329d386c85 100644 --- a/drivers/bus/pci/version.map +++ b/drivers/bus/pci/version.map @@ -38,4 +38,5 @@ INTERNAL { rte_pci_get_sysfs_path; rte_pci_register; rte_pci_unregister; + rte_pci_set_pasid; }; diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h index 69e932d910..772a8d5622 100644 --- a/lib/pci/rte_pci.h +++ b/lib/pci/rte_pci.h @@ -101,6 +101,11 @@ extern "C" { #define RTE_PCI_EXT_CAP_ID_ACS 0x0d /* Access Control Services */ #define RTE_PCI_EXT_CAP_ID_SRIOV 0x10 /* SR-IOV */ #define RTE_PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ +#define RTE_PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ + +/* Process Address Space ID */ +#define RTE_PCI_PASID_CTRL 0x06 /* PASID control register */ +#define RTE_PCI_PASID_CAP_OFFSET 0x148 /* PASID capability offset */ /* Advanced Error Reporting (RTE_PCI_EXT_CAP_ID_ERR) */ #define RTE_PCI_ERR_UNCOR_STATUS 0x04 /* Uncorrectable Error Status */