From patchwork Fri Nov 3 18:29:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sevincer, Abdullah" X-Patchwork-Id: 133852 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 24ADC4327C; Fri, 3 Nov 2023 19:29:52 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 830D642DE9; Fri, 3 Nov 2023 19:29:42 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 8164A42DC3; Fri, 3 Nov 2023 19:29:40 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699036180; x=1730572180; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IOyAk5GwxmDqdL/YB+pc3H4OcHdzkHfiQfsZ7gf+Wwo=; b=KfKH03pA9Ttm0AlK6wIlLLqfxJOccpVvADSurssVrwn71Gui0okDrpYi ujkm+HCMEW+RzY43peMtdMQ3/8kYH3Se2CzxT9s0eerLnfnt8G5M4MtEB YuanUt7MCqigd0kiIFtyP8Kwy70pEO6AGcZiz8NCU5j88A/UhQ/2EtXhJ hxugAv2yuwoGHLQnDbXr4vyjuJXhnZAG610WWTTJz7cL3bGR/bq9UYOSZ Q7wyrkNH2Si6MF+zCIWgAdMpkPiqKmTZ2yehuIHS4BgcCL6JDBwKw7eVz yeIY98j+oTYisyWWjttTklrItWoRP6jSK8ssTuhUJ12Qra/BjNnu4Yvvv w==; X-IronPort-AV: E=McAfee;i="6600,9927,10883"; a="391867092" X-IronPort-AV: E=Sophos;i="6.03,273,1694761200"; d="scan'208";a="391867092" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2023 11:29:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.03,273,1694761200"; d="scan'208";a="9465881" Received: from txanpdk02.an.intel.com ([10.123.117.76]) by orviesa001.jf.intel.com with ESMTP; 03 Nov 2023 11:29:39 -0700 From: Abdullah Sevincer To: dev@dpdk.org Cc: jerinj@marvell.com, mike.ximing.chen@intel.com, bruce.richardson@intel.com, thomas@monjalon.net, Abdullah Sevincer , stable@dpdk.org Subject: [PATCH v6 2/2] event/dlb2: fix disable PASID Date: Fri, 3 Nov 2023 13:29:33 -0500 Message-Id: <20231103182933.2831662-3-abdullah.sevincer@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231103182933.2831662-1-abdullah.sevincer@intel.com> References: <20231103182933.2831662-1-abdullah.sevincer@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org In vfio-pci driver when PASID is enabled by default DLB hardware puts DLB in SIOV mode. This breaks DLB PF-PMD mode. For DLB PF-PMD mode to function properly PASID needs to be disabled. In this commit this issue is addressed and PASID is disabled by writing a zero to PASID control register. Fixes: 5433956d5185 ("event/dlb2: add eventdev probe") Cc: stable@dpdk.org Signed-off-by: Abdullah Sevincer --- drivers/event/dlb2/pf/dlb2_main.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c index aa03e4c311..05c2354515 100644 --- a/drivers/event/dlb2/pf/dlb2_main.c +++ b/drivers/event/dlb2/pf/dlb2_main.c @@ -26,6 +26,7 @@ #define PF_ID_ZERO 0 /* PF ONLY! */ #define NO_OWNER_VF 0 /* PF ONLY! */ #define NOT_VF_REQ false /* PF ONLY! */ +#define DLB2_PCI_PASID_CAP_OFFSET 0x148 /* PASID capability offset */ static int dlb2_pf_init_driver_state(struct dlb2_dev *dlb2_dev) @@ -514,6 +515,16 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) } } + /* Disable PASID if it is enabled by default, which + * breaks the DLB if enabled. + */ + off = DLB2_PCI_PASID_CAP_OFFSET + RTE_PCI_PASID_CTRL; + if (rte_pci_pasid_ena_dis(pdev, off, false)) { + DLB2_LOG_ERR("[%s()] failed to write the pcie config space at offset %d\n", + __func__, (int)off); + return -1; + } + return 0; }