From patchwork Mon Nov 13 12:41:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bing Zhao X-Patchwork-Id: 134155 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 129E6432D3; Mon, 13 Nov 2023 13:42:01 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F2E53402F2; Mon, 13 Nov 2023 13:42:00 +0100 (CET) Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2057.outbound.protection.outlook.com [40.107.237.57]) by mails.dpdk.org (Postfix) with ESMTP id 871FC4026C; Mon, 13 Nov 2023 13:41:59 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=AuwpP8sa2QiKv1wBBc6/e4HwqO6lsCnmlyMSVhRR2QZr1DYM5FG2GkA4w3JNKt5O/ZMwrJJA4ypTWHoOixZVL5rUOR02J4diGBJ0ztLZw/ahno4Fpr4T/lNzGJ/EzCCNNuZ+Tu41Xl8MP4fYmOZUd3tmt6hluclEIH/tgAk1oAO9nrkKB6XbxuySEDSurDm7BaeWWQtm61MQSYtpillb9SFaYGD7K5u+m9Z26C3DfhBe+hIp/EdNwzKu5WLM66aqj04PISbNMgJcLBLdzIZwWe9BOuHZ7swHWhccYjNvrBLnYOzlwdVjVLrvVi1ImrOUOkCvoxuvMePno8ht4XbMvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=sT8x0OsdQpLd+RQjQZo13CH1WS//7dRXtdn0j/00IGA=; b=Pw1FFTokdFtA0/pzRSLt67xx5GX5RxOmWibXowzgObCUQxi8QXatyXhxg4xKbc1+N9UD5omXeZkK2O8R0t3utjv+7P8fH+7rZASIPb8T2zPhwTNildYFhQesj4ttdd+Pjj18hc2QUWQku351jbXpLF12st0Ohfsosw1m99+Cu6ojx90RXHbJxJQfrVZLEs48DOot0UROCm+vC+ZRTo8BbptXuCxElYjLwzuDaH8mjR07mGZSP9RW1gLZeV9QD37BUife5Gn+JVqJBPx4ay7nbBSxC95/+C4InqzdCJBZOe0it9nr6gb7XynefNeAuN+9BRo8Ali/p9DElJxDTgF8yg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=sT8x0OsdQpLd+RQjQZo13CH1WS//7dRXtdn0j/00IGA=; b=XzjJhcMC5WFyg/jbNL3MMvnt5zwYuecqTF/5KPQjc2gEwfGxCKj07rsauhAiEB4tdCCgzl0APNQqK/4SxRbBWHdhvlYTm1TXTrzP75OtR7PS31YK6iqIbAi/iiAUiyimZ3nwMtTeUVcuL6901ykd6Giyaan+Cow1jAfJp7gjpdsyS8xlLpiBbNzj9fbBGwVO1BS2RxQ0yxCnCK2baEJHFT5wAKIrV45DzSp/CSw0QIoTEeMFUC+hIcAzi/wgA3oGn5IiML94GJq0o2wltqCvqjqhJdq1s85knMo1zuSI82a4Cn/O675txzl1iwT6j8iNs+H2w69HPGGpnNSMasmJFw== Received: from CY8PR12CA0042.namprd12.prod.outlook.com (2603:10b6:930:49::21) by DM6PR12MB4481.namprd12.prod.outlook.com (2603:10b6:5:2af::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6977.31; Mon, 13 Nov 2023 12:41:56 +0000 Received: from CY4PEPF0000FCC3.namprd03.prod.outlook.com (2603:10b6:930:49:cafe::8b) by CY8PR12CA0042.outlook.office365.com (2603:10b6:930:49::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6977.31 via Frontend Transport; Mon, 13 Nov 2023 12:41:56 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000FCC3.mail.protection.outlook.com (10.167.242.105) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7002.13 via Frontend Transport; Mon, 13 Nov 2023 12:41:55 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 13 Nov 2023 04:41:54 -0800 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 13 Nov 2023 04:41:51 -0800 From: Bing Zhao To: , , , , CC: , , Subject: [PATCH] net/mlx5: fix the LACP redirection in Rx domain Date: Mon, 13 Nov 2023 14:41:36 +0200 Message-ID: <20231113124136.8071-1-bingz@nvidia.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000FCC3:EE_|DM6PR12MB4481:EE_ X-MS-Office365-Filtering-Correlation-Id: 27d437e2-123b-49c5-ac02-08dbe445ebb5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: H1a01g4Nm8zyc4YLxoZjWbMsh58drUJriY1wkr6FdBTvZKZgm0NvHbLZ7aEQhN7PIRg4nJXmZ1OdyNqwYazoZAUK0BgLoOtQzDExI0wnt0VeNJHcKzpDJ0BjWaiCZesqPFisFhT1DMMZGS5Tof/5V/QMHjoFvZV9Yw2H+1Fqmx4LcPF3t5irJWQIW9gai7G4/ikbacKWnn3UWe9Vm09I4xACfxLIaeYmrpCKRSXQQhwEQUcvfKRs1kJ97IixdRjgUjVeYAvar3LwGetv/FdgN4OzRvFkhYcMFP0gLUKdL5omBQRnR/hL0Cv1/pYkEj6Whw84+1Tlu2dTaQGbV0CXRRSD7XxBkTE0lR7+ogJcvVRvbwwRVl8WN8ZZpS47GRfFJpoDX680wWWQJWGgtOJqTiMlQomTjvYiARb25wVqoyy0PQ003k9Py1rt82QXH2bA7WEBn4JPKITSnniIhcAKsoFGDup4Hjsv/XlMf45fvdRDvaKQQkV9JI7LJbBikgTW8Cox8AU308DhSJHIdjXFGx3pnVpp976mdGar4gmiTqFWCwSARlUt3s+kdvXnNGbp7g2NlBKbRaMn3x/C0NO3wZ1AiB3rsVij4loMzqdx9f3brMHHOI1hY22vn1F4LX+ZDYQMsOY+a/xQtlGCzj/FLZr1SGNTX7KOWfXICx+pfAtX9N0YQYib7xLbl7FVQZ3wEAW42IVNglnC+kUx3TmEEfWFySBTKLwJ/imClbOEd6mbAGxj8iWfzKk4HA5v1NHsY673SITWIJOUuvH8bWw0hVyWtp8OOw786drRi1xVEdY= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230031)(4636009)(39860400002)(346002)(396003)(376002)(136003)(230922051799003)(230273577357003)(230173577357003)(451199024)(82310400011)(186009)(1800799009)(64100799003)(46966006)(36840700001)(40470700004)(36756003)(36860700001)(7636003)(356005)(426003)(336012)(41300700001)(40460700003)(83380400001)(47076005)(4326008)(7696005)(30864003)(1076003)(40480700001)(70206006)(70586007)(110136005)(55016003)(54906003)(316002)(6636002)(2616005)(5660300002)(86362001)(8936002)(6666004)(450100002)(478600001)(8676002)(6286002)(26005)(16526019)(82740400003)(2906002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Nov 2023 12:41:55.9922 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 27d437e2-123b-49c5-ac02-08dbe445ebb5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4481 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When the "lacp_by_user" is not set from the application in bond mode, the LACP traffic should be handled by the kernel driver by default. This commit adds the missing support in the template API when "dv_flow_en=2". The behavior will be the same as that in the DV mode with "dv_flow_en=1". The LACP packets will be redirected to the kernel when starting the steering in the NIC Rx domain. With this commit, the DEFAULT_MISS action usage is refactored a bit. In the HWS, one unique action can be created with supported bits set in the "flag" per port. The *ROOT_FDB and *HWS_FDB flag bits will only be set when the port is in switchdev mode and working as the E-Switch manager proxy port. The SF/VF and all other representors won't have the FDB flag bits when creating the DEFAULT_MISS action. Fixes: 9fa7c1cddb85 ("net/mlx5: create control flow rules with HWS") Cc: dsosnowski@nvidia.com Cc: stable@dpdk.org Signed-off-by: Bing Zhao Acked-by: Suanming Mou --- drivers/net/mlx5/linux/mlx5_os.c | 8 +- drivers/net/mlx5/mlx5.h | 1 + drivers/net/mlx5/mlx5_flow.h | 1 + drivers/net/mlx5/mlx5_flow_hw.c | 249 +++++++++++++++++++++++++++++-- drivers/net/mlx5/mlx5_trigger.c | 3 + 5 files changed, 249 insertions(+), 13 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 07f31de5ae..ae82e1e5d8 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -474,6 +474,10 @@ mlx5_alloc_shared_dr(struct mlx5_priv *priv) err = mlx5_alloc_table_hash_list(priv); if (err) goto error; + sh->default_miss_action = + mlx5_glue->dr_create_flow_action_default_miss(); + if (!sh->default_miss_action) + DRV_LOG(WARNING, "Default miss action is not supported."); /* The resources below are only valid with DV support. */ #ifdef HAVE_IBV_FLOW_DV_SUPPORT /* Init shared flex parsers list, no need lcore_share */ @@ -600,10 +604,6 @@ mlx5_alloc_shared_dr(struct mlx5_priv *priv) __mlx5_discovery_misc5_cap(priv); #endif /* HAVE_MLX5DV_DR */ - sh->default_miss_action = - mlx5_glue->dr_create_flow_action_default_miss(); - if (!sh->default_miss_action) - DRV_LOG(WARNING, "Default miss action is not supported."); LIST_INIT(&sh->shared_rxqs); return 0; error: diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 795748eddc..f0d63a0ba5 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1860,6 +1860,7 @@ struct mlx5_priv { struct rte_flow_template_table *hw_esw_sq_miss_tbl; struct rte_flow_template_table *hw_esw_zero_tbl; struct rte_flow_template_table *hw_tx_meta_cpy_tbl; + struct rte_flow_template_table *hw_lacp_rx_tbl; struct rte_flow_pattern_template *hw_tx_repr_tagging_pt; struct rte_flow_actions_template *hw_tx_repr_tagging_at; struct rte_flow_template_table *hw_tx_repr_tagging_tbl; diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 8c0b9a4b60..6dde9de688 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -2880,6 +2880,7 @@ int mlx5_flow_hw_esw_destroy_sq_miss_flow(struct rte_eth_dev *dev, int mlx5_flow_hw_esw_create_default_jump_flow(struct rte_eth_dev *dev); int mlx5_flow_hw_create_tx_default_mreg_copy_flow(struct rte_eth_dev *dev); int mlx5_flow_hw_tx_repr_matching_flow(struct rte_eth_dev *dev, uint32_t sqn, bool external); +int mlx5_flow_hw_lacp_rx_flow(struct rte_eth_dev *dev); int mlx5_flow_actions_validate(struct rte_eth_dev *dev, const struct rte_flow_actions_template_attr *attr, const struct rte_flow_action actions[], diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index c35064518a..d72f0a66fb 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -2454,6 +2454,15 @@ __flow_hw_actions_translate(struct rte_eth_dev *dev, dr_pos)) goto err; break; + case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS: + /* Internal, can be skipped. */ + if (!!attr->group) { + DRV_LOG(ERR, "DEFAULT MISS action is only" + " supported in root table."); + goto err; + } + acts->rule_acts[dr_pos].action = priv->hw_def_miss; + break; case RTE_FLOW_ACTION_TYPE_END: actions_end = true; break; @@ -5531,6 +5540,34 @@ flow_hw_validate_action_push_vlan(struct rte_eth_dev *dev, #undef X_FIELD } +static int +flow_hw_validate_action_default_miss(struct rte_eth_dev *dev, + const struct rte_flow_actions_template_attr *attr, + uint64_t action_flags, + struct rte_flow_error *error) +{ + /* + * The private DEFAULT_MISS action is used internally for LACP in control + * flows. So this validation can be ignored. It can be kept right now since + * the validation will be done only once. + */ + struct mlx5_priv *priv = dev->data->dev_private; + + if (!attr->ingress || attr->egress || attr->transfer) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, NULL, + "DEFAULT MISS is only supported in ingress."); + if (!priv->hw_def_miss) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, NULL, + "DEFAULT MISS action does not exist."); + if (action_flags & MLX5_FLOW_FATE_ACTIONS) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, NULL, + "DEFAULT MISS should be the only termination."); + return 0; +} + static int mlx5_flow_hw_actions_validate(struct rte_eth_dev *dev, const struct rte_flow_actions_template_attr *attr, @@ -5568,7 +5605,7 @@ mlx5_flow_hw_actions_validate(struct rte_eth_dev *dev, RTE_FLOW_ERROR_TYPE_ACTION, action, "mask type does not match action type"); - switch (action->type) { + switch ((int)action->type) { case RTE_FLOW_ACTION_TYPE_VOID: break; case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST: @@ -5735,6 +5772,13 @@ mlx5_flow_hw_actions_validate(struct rte_eth_dev *dev, case RTE_FLOW_ACTION_TYPE_END: actions_end = true; break; + case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS: + ret = flow_hw_validate_action_default_miss(dev, attr, + action_flags, error); + if (ret < 0) + return ret; + action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS; + break; default: return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, @@ -5754,8 +5798,7 @@ flow_hw_actions_validate(struct rte_eth_dev *dev, const struct rte_flow_action masks[], struct rte_flow_error *error) { - return mlx5_flow_hw_actions_validate(dev, attr, actions, masks, NULL, - error); + return mlx5_flow_hw_actions_validate(dev, attr, actions, masks, NULL, error); } @@ -5907,7 +5950,7 @@ flow_hw_dr_actions_template_create(struct rte_eth_dev *dev, if (curr_off >= MLX5_HW_MAX_ACTS) goto err_actions_num; - switch (at->actions[i].type) { + switch ((int)at->actions[i].type) { case RTE_FLOW_ACTION_TYPE_VOID: break; case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST: @@ -5998,6 +6041,10 @@ flow_hw_dr_actions_template_create(struct rte_eth_dev *dev, } at->dr_off[i] = cnt_off; break; + case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS: + at->dr_off[i] = curr_off; + action_types[curr_off++] = MLX5DR_ACTION_TYP_MISS; + break; default: type = mlx5_hw_dr_action_types[at->actions[i].type]; at->dr_off[i] = curr_off; @@ -7773,6 +7820,42 @@ flow_hw_create_tx_default_mreg_copy_pattern_template(struct rte_eth_dev *dev, return flow_hw_pattern_template_create(dev, &tx_pa_attr, eth_all, error); } +/* + * Creating a flow pattern template with all LACP packets matching, only for NIC + * ingress domain. + * + * @param dev + * Pointer to Ethernet device. + * @param error + * Pointer to error structure. + * + * @return + * Pointer to flow pattern template on success, NULL otherwise. + */ +static struct rte_flow_pattern_template * +flow_hw_create_lacp_rx_pattern_template(struct rte_eth_dev *dev, struct rte_flow_error *error) +{ + struct rte_flow_pattern_template_attr pa_attr = { + .relaxed_matching = 0, + .ingress = 1, + }; + struct rte_flow_item_eth lacp_mask = { + .dst.addr_bytes = "\x00\x00\x00\x00\x00\x00", + .src.addr_bytes = "\x00\x00\x00\x00\x00\x00", + .type = 0xFFFF, + }; + struct rte_flow_item eth_all[] = { + [0] = { + .type = RTE_FLOW_ITEM_TYPE_ETH, + .mask = &lacp_mask, + }, + [1] = { + .type = RTE_FLOW_ITEM_TYPE_END, + }, + }; + return flow_hw_pattern_template_create(dev, &pa_attr, eth_all, error); +} + /** * Creates a flow actions template with modify field action and masked jump action. * Modify field action sets the least significant bit of REG_C_0 (usable by user-space) @@ -8042,6 +8125,38 @@ flow_hw_create_tx_default_mreg_copy_actions_template(struct rte_eth_dev *dev, masks, error); } +/* + * Creating an actions template to use default miss to re-route packets to the + * kernel driver stack. + * On root table, only DEFAULT_MISS action can be used. + * + * @param dev + * Pointer to Ethernet device. + * @param error + * Pointer to error structure. + * + * @return + * Pointer to flow actions template on success, NULL otherwise. + */ +static struct rte_flow_actions_template * +flow_hw_create_lacp_rx_actions_template(struct rte_eth_dev *dev, struct rte_flow_error *error) +{ + struct rte_flow_actions_template_attr act_attr = { + .ingress = 1, + }; + const struct rte_flow_action actions[] = { + [0] = { + .type = (enum rte_flow_action_type) + MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS, + }, + [1] = { + .type = RTE_FLOW_ACTION_TYPE_END, + }, + }; + + return flow_hw_actions_template_create(dev, &act_attr, actions, actions, error); +} + /** * Creates a control flow table used to transfer traffic from E-Switch Manager * and TX queues from group 0 to group 1. @@ -8200,6 +8315,43 @@ flow_hw_create_ctrl_jump_table(struct rte_eth_dev *dev, return flow_hw_table_create(dev, &cfg, &it, 1, &at, 1, error); } +/* + * Create a table on the root group to for the LACP traffic redirecting. + * + * @param dev + * Pointer to Ethernet device. + * @param it + * Pointer to flow pattern template. + * @param at + * Pointer to flow actions template. + * + * @return + * Pointer to flow table on success, NULL otherwise. + */ +static struct rte_flow_template_table * +flow_hw_create_lacp_rx_table(struct rte_eth_dev *dev, + struct rte_flow_pattern_template *it, + struct rte_flow_actions_template *at, + struct rte_flow_error *error) +{ + struct rte_flow_template_table_attr attr = { + .flow_attr = { + .group = 0, + .priority = 0, + .ingress = 1, + .egress = 0, + .transfer = 0, + }, + .nb_flows = 1, + }; + struct mlx5_flow_template_table_cfg cfg = { + .attr = attr, + .external = false, + }; + + return flow_hw_table_create(dev, &cfg, &it, 1, &at, 1, error); +} + /** * Creates a set of flow tables used to create control flows used * when E-Switch is engaged. @@ -8220,10 +8372,12 @@ flow_hw_create_ctrl_tables(struct rte_eth_dev *dev, struct rte_flow_error *error struct rte_flow_pattern_template *regc_sq_items_tmpl = NULL; struct rte_flow_pattern_template *port_items_tmpl = NULL; struct rte_flow_pattern_template *tx_meta_items_tmpl = NULL; + struct rte_flow_pattern_template *lacp_rx_items_tmpl = NULL; struct rte_flow_actions_template *regc_jump_actions_tmpl = NULL; struct rte_flow_actions_template *port_actions_tmpl = NULL; struct rte_flow_actions_template *jump_one_actions_tmpl = NULL; struct rte_flow_actions_template *tx_meta_actions_tmpl = NULL; + struct rte_flow_actions_template *lacp_rx_actions_tmpl = NULL; uint32_t xmeta = priv->sh->config.dv_xmeta_en; uint32_t repr_matching = priv->sh->config.repr_matching; int ret; @@ -8319,6 +8473,28 @@ flow_hw_create_ctrl_tables(struct rte_eth_dev *dev, struct rte_flow_error *error goto err; } } + /* Create LACP default miss table. */ + if (!priv->sh->config.lacp_by_user && priv->pf_bond >= 0) { + lacp_rx_items_tmpl = flow_hw_create_lacp_rx_pattern_template(dev, error); + if (!lacp_rx_items_tmpl) { + DRV_LOG(ERR, "port %u failed to create pattern template" + " for LACP Rx traffic", dev->data->port_id); + goto err; + } + lacp_rx_actions_tmpl = flow_hw_create_lacp_rx_actions_template(dev, error); + if (!lacp_rx_actions_tmpl) { + DRV_LOG(ERR, "port %u failed to create actions template" + " for LACP Rx traffic", dev->data->port_id); + goto err; + } + priv->hw_lacp_rx_tbl = flow_hw_create_lacp_rx_table(dev, lacp_rx_items_tmpl, + lacp_rx_actions_tmpl, error); + if (!priv->hw_lacp_rx_tbl) { + DRV_LOG(ERR, "port %u failed to create template table for" + " for LACP Rx traffic", dev->data->port_id); + goto err; + } + } return 0; err: /* Do not overwrite the rte_errno. */ @@ -8327,6 +8503,10 @@ flow_hw_create_ctrl_tables(struct rte_eth_dev *dev, struct rte_flow_error *error ret = rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, "Failed to create control tables."); + if (priv->hw_tx_meta_cpy_tbl) { + flow_hw_table_destroy(dev, priv->hw_tx_meta_cpy_tbl, NULL); + priv->hw_tx_meta_cpy_tbl = NULL; + } if (priv->hw_esw_zero_tbl) { flow_hw_table_destroy(dev, priv->hw_esw_zero_tbl, NULL); priv->hw_esw_zero_tbl = NULL; @@ -8339,6 +8519,8 @@ flow_hw_create_ctrl_tables(struct rte_eth_dev *dev, struct rte_flow_error *error flow_hw_table_destroy(dev, priv->hw_esw_sq_miss_root_tbl, NULL); priv->hw_esw_sq_miss_root_tbl = NULL; } + if (lacp_rx_actions_tmpl) + flow_hw_actions_template_destroy(dev, lacp_rx_actions_tmpl, NULL); if (tx_meta_actions_tmpl) flow_hw_actions_template_destroy(dev, tx_meta_actions_tmpl, NULL); if (jump_one_actions_tmpl) @@ -8347,6 +8529,8 @@ flow_hw_create_ctrl_tables(struct rte_eth_dev *dev, struct rte_flow_error *error flow_hw_actions_template_destroy(dev, port_actions_tmpl, NULL); if (regc_jump_actions_tmpl) flow_hw_actions_template_destroy(dev, regc_jump_actions_tmpl, NULL); + if (lacp_rx_items_tmpl) + flow_hw_pattern_template_destroy(dev, lacp_rx_items_tmpl, NULL); if (tx_meta_items_tmpl) flow_hw_pattern_template_destroy(dev, tx_meta_items_tmpl, NULL); if (port_items_tmpl) @@ -8998,6 +9182,7 @@ flow_hw_configure(struct rte_eth_dev *dev, struct rte_flow_queue_attr ctrl_queue_attr = {0}; bool is_proxy = !!(priv->sh->config.dv_esw_en && priv->master); int ret = 0; + uint32_t action_flags; if (!port_attr || !nb_queue || !queue_attr) { rte_errno = EINVAL; @@ -9229,12 +9414,21 @@ flow_hw_configure(struct rte_eth_dev *dev, if (ret) goto err; } + /* + * DEFAULT_MISS action have different behaviors in different domains. + * In FDB, it will steering the packets to the E-switch manager. + * In NIC Rx root, it will steering the packet to the kernel driver stack. + * An action with all bits set in the flag can be created and the HWS + * layer will translate it properly when being used in different rules. + */ + action_flags = MLX5DR_ACTION_FLAG_ROOT_RX | MLX5DR_ACTION_FLAG_HWS_RX | + MLX5DR_ACTION_FLAG_ROOT_TX | MLX5DR_ACTION_FLAG_HWS_TX; + if (is_proxy) + action_flags |= (MLX5DR_ACTION_FLAG_ROOT_FDB | MLX5DR_ACTION_FLAG_HWS_FDB); + priv->hw_def_miss = mlx5dr_action_create_default_miss(priv->dr_ctx, action_flags); + if (!priv->hw_def_miss) + goto err; if (is_proxy) { - /* Only supported on proxy port. */ - priv->hw_def_miss = mlx5dr_action_create_default_miss - (priv->dr_ctx, MLX5DR_ACTION_FLAG_HWS_FDB); - if (!priv->hw_def_miss) - goto err; ret = flow_hw_create_vport_actions(priv); if (ret) { rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, @@ -11956,6 +12150,43 @@ mlx5_flow_hw_tx_repr_matching_flow(struct rte_eth_dev *dev, uint32_t sqn, bool e items, 0, actions, 0, &flow_info, external); } +int +mlx5_flow_hw_lacp_rx_flow(struct rte_eth_dev *dev) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct rte_flow_item_eth lacp_item = { + .type = RTE_BE16(RTE_ETHER_TYPE_SLOW), + }; + struct rte_flow_item eth_lacp[] = { + [0] = { + .type = RTE_FLOW_ITEM_TYPE_ETH, + .spec = &lacp_item, + .mask = &lacp_item, + }, + [1] = { + .type = RTE_FLOW_ITEM_TYPE_END, + }, + }; + struct rte_flow_action miss_action[] = { + [0] = { + .type = (enum rte_flow_action_type) + MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS, + }, + [1] = { + .type = RTE_FLOW_ACTION_TYPE_END, + }, + }; + struct mlx5_hw_ctrl_flow_info flow_info = { + .type = MLX5_HW_CTRL_FLOW_TYPE_LACP_RX, + }; + + MLX5_ASSERT(priv->master); + if (!priv->dr_ctx || !priv->hw_lacp_rx_tbl) + return 0; + return flow_hw_create_ctrl_flow(dev, dev, priv->hw_lacp_rx_tbl, eth_lacp, 0, + miss_action, 0, &flow_info, false); +} + static uint32_t __calc_pattern_flags(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type) { diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c index 35733b0604..5ac25d7e2d 100644 --- a/drivers/net/mlx5/mlx5_trigger.c +++ b/drivers/net/mlx5/mlx5_trigger.c @@ -1524,6 +1524,9 @@ mlx5_traffic_enable_hws(struct rte_eth_dev *dev) } if (priv->isolated) return 0; + if (!priv->sh->config.lacp_by_user && priv->pf_bond >= 0) + if (mlx5_flow_hw_lacp_rx_flow(dev)) + goto error; if (dev->data->promiscuous) flags |= MLX5_CTRL_PROMISCUOUS; if (dev->data->all_multicast)