From patchwork Mon Nov 13 17:27:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sevincer, Abdullah" X-Patchwork-Id: 134177 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B71734331D; Mon, 13 Nov 2023 18:28:05 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 80C7B4026F; Mon, 13 Nov 2023 18:28:05 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id 9287E4026C for ; Mon, 13 Nov 2023 18:28:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699896483; x=1731432483; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=H3CB1clKH5Vdkopinoj9wgvGD5xaXt6Y6N368Ow2GFg=; b=JXsAoysbfPNywf67hN1eB20daLzo+5vsZlhOCdvdFZjaCqV3SrpuTEYS vL6I4bbJvNPSm08Sy7UXdf+qeLlnlMWUKibze2HlOlFcjo97NSEJFLvKI 1SqL8QuMEbflVjktx6/c1grjQJ43AcFjxuymi0ONLzTY01mOc+tcr84zy HGBBjloxLG/GaNx5YfNNEvOJylVqvsiBmCCLo34gekXyMKaYAk2+8hI48 jPtvvrlhsFSYKqxfLUN5POnOvwrfvltmKiqM1ASBMNX/kfw7qKl+gzAeJ ehQ+B2WeC2bnVrgyjCODhmA82CYRtklSVTTYCoPCu3ZZMFEAjwRrFv3jB g==; X-IronPort-AV: E=McAfee;i="6600,9927,10893"; a="375505778" X-IronPort-AV: E=Sophos;i="6.03,299,1694761200"; d="scan'208";a="375505778" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2023 09:28:02 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.03,299,1694761200"; d="scan'208";a="5719674" Received: from txanpdk02.an.intel.com ([10.123.117.76]) by fmviesa002.fm.intel.com with ESMTP; 13 Nov 2023 09:28:02 -0800 From: Abdullah Sevincer To: dev@dpdk.org Cc: jerinj@marvell.com, mike.ximing.chen@intel.com, bruce.richardson@intel.com, thomas@monjalon.net, david.marchand@redhat.com, Abdullah Sevincer Subject: [PATCH v1] bus/pci: revise support PASID control Date: Mon, 13 Nov 2023 11:27:59 -0600 Message-Id: <20231113172759.3529518-1-abdullah.sevincer@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231106170521.3064038-2-abdullah.sevincer@intel.com> References: <20231106170521.3064038-2-abdullah.sevincer@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This commit revises PASID control function to accept PASID offset to pasid *structure* instead of taking exact register for controlling the feature. PASID control function was introduced in earlier commit. Pls see commit 5a6878335b81 ("event/dlb2: disable PASID") and commit 60ea19609aec ("bus/pci: add PASID control"). Signed-off-by: Abdullah Sevincer --- drivers/bus/pci/pci_common.c | 5 ++--- drivers/bus/pci/rte_bus_pci.h | 5 ++++- drivers/event/dlb2/pf/dlb2_main.c | 4 ++-- lib/pci/rte_pci.h | 2 +- 4 files changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/bus/pci/pci_common.c b/drivers/bus/pci/pci_common.c index ba5e280d33..dbe647d15d 100644 --- a/drivers/bus/pci/pci_common.c +++ b/drivers/bus/pci/pci_common.c @@ -943,9 +943,8 @@ rte_pci_pasid_set_state(const struct rte_pci_device *dev, off_t offset, bool enable) { uint16_t pasid = enable; - return rte_pci_write_config(dev, &pasid, sizeof(pasid), offset) < 0 - ? -1 - : 0; + return rte_pci_write_config(dev, &pasid, sizeof(pasid), + offset + RTE_PCI_PASID_CTRL) < 0 ? -1 : 0; } struct rte_pci_bus rte_pci_bus = { diff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h index f07bf9b588..35d07d8294 100644 --- a/drivers/bus/pci/rte_bus_pci.h +++ b/drivers/bus/pci/rte_bus_pci.h @@ -161,9 +161,12 @@ int rte_pci_set_bus_master(const struct rte_pci_device *dev, bool enable); * @param dev * A pointer to a rte_pci_device structure. * @param offset - * Offset of the PASID external capability. + * Offset of the PASID external capability structure. * @param enable * Flag to enable or disable PASID. + * + * @return + * 0 on success, -1 on error in PCI config space read/write. */ __rte_internal int rte_pci_pasid_set_state(const struct rte_pci_device *dev, diff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c index 61a7b39eef..a95d3227a4 100644 --- a/drivers/event/dlb2/pf/dlb2_main.c +++ b/drivers/event/dlb2/pf/dlb2_main.c @@ -518,8 +518,8 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) /* Disable PASID if it is enabled by default, which * breaks the DLB if enabled. */ - off = DLB2_PCI_PASID_CAP_OFFSET + RTE_PCI_PASID_CTRL; - if (rte_pci_pasid_set_state(pdev, off, false)) { + off = DLB2_PCI_PASID_CAP_OFFSET; + if (rte_pci_pasid_set_state(pdev, off, false) < 0) { DLB2_LOG_ERR("[%s()] failed to write the pcie config space at offset %d\n", __func__, (int)off); return -1; diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h index 0d2d8d8fed..c26fc77209 100644 --- a/lib/pci/rte_pci.h +++ b/lib/pci/rte_pci.h @@ -101,7 +101,7 @@ extern "C" { #define RTE_PCI_EXT_CAP_ID_ACS 0x0d /* Access Control Services */ #define RTE_PCI_EXT_CAP_ID_SRIOV 0x10 /* SR-IOV */ #define RTE_PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ -#define RTE_PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ +#define RTE_PCI_EXT_CAP_ID_PASID 0x1b /* Process Address Space ID */ /* Advanced Error Reporting (RTE_PCI_EXT_CAP_ID_ERR) */ #define RTE_PCI_ERR_UNCOR_STATUS 0x04 /* Uncorrectable Error Status */