From patchwork Sun Dec 3 11:25:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 134747 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 518B243660; Sun, 3 Dec 2023 12:26:16 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F38C04028C; Sun, 3 Dec 2023 12:26:14 +0100 (CET) Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2063.outbound.protection.outlook.com [40.107.223.63]) by mails.dpdk.org (Postfix) with ESMTP id AA8C64027B; Sun, 3 Dec 2023 12:26:13 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Q8TrE5v3Ddf44v6TdAIQYMYkOGnbunUH4uzMkv8lpmCdDdMaxq0ZBJHr1epKHtrPBQ7RIQS5/4/wvJRx/Gr+0kAkLKWKb+nt3ZbMwqq89S2KQ2ax/dK8UeIrzjcjWy91vn+JBacG/G9GmHQBD2Bq+MayeFWwEtjKCp4zf+DSNfP7LmLLcJ/3Ht0zRyFD1KG3FPJ1YSyDDsSEoCLbWiMdxvMoEZQn+tVE0CeOg9SAjvHQAH2yugM9MBfYsYqDMVU+iFWyJHSuNrB/N+EHhOTgnaKfo0ndpNIurI6TH3b3kCy0vlw0D70a1WbPBnD2VHWIJqPU+gl/VkNnL7invHvYog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=0fV1SQ0GSegdEKhluA5bRl8GrAwXf8x+Rdt9kdFS0jA=; b=UuqzSE3nh3KtznJij34DFyKorsICQ7+oaZhl/7gIsU9/liFN9lT8M3k5LeuJDcyxwKAQ5tsykDw24m2kqhQkZc5Ptsttqqk2z7q2aJ8cymx8wOdeW72kXOMwVJhIP+ACtwrUm0p5XwUe45fiGSouW7rLO2aLXFrIgInA7PpEb/JpToAv4WVZhyI+Ns6uVTpFl3HMxLMXSUE4POUez+ru/eEyUbUx4cL4SMUsfytrerYt6AwD/UMoKwQqYa2et2nca7NH3o5bkH2suRhKpJke0ACpft3Q22mHxa7R2YP7Wq9vxGPOE7H91Ze2cpU0mSs/6n98g6bdloo/441yaDfPQg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0fV1SQ0GSegdEKhluA5bRl8GrAwXf8x+Rdt9kdFS0jA=; b=V3Ckced+ETUdqwm/Fy0/f7siM7qi3Hwkgl6cK7FOLXZqHhRT0n00CnKrw4Xm1u8uyHymXjehJou2WZOi6rNOUHcGCtXLN1GS8SVgYqSH3XaygcglSfxE5MFopneTdF3TH4jslNrtyjt3HfM4MV4ApkYuepfpSUiihTebr0bhxxwe72gNNBbCI6OXfv+1HFHVF0pj4IVEbIJblYihNlD/TcsMR+y991Zs3+yM7fRrRz7uyAWKXrL+QsxKJKG9QLMRjWSOeOuwKfJ/bfv8hFSobypB6GtXkw1iEPXqn93L2Jt4SZ2stK0D3Eo1tEZ1aVvaMUgwaSTI8CTRjfsf6bGVmA== Received: from DM6PR21CA0022.namprd21.prod.outlook.com (2603:10b6:5:174::32) by CY5PR12MB6646.namprd12.prod.outlook.com (2603:10b6:930:41::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.32; Sun, 3 Dec 2023 11:26:10 +0000 Received: from DS1PEPF00017098.namprd05.prod.outlook.com (2603:10b6:5:174:cafe::a8) by DM6PR21CA0022.outlook.office365.com (2603:10b6:5:174::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6977.16 via Frontend Transport; Sun, 3 Dec 2023 11:26:10 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DS1PEPF00017098.mail.protection.outlook.com (10.167.18.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.20 via Frontend Transport; Sun, 3 Dec 2023 11:26:10 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Sun, 3 Dec 2023 03:25:58 -0800 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Sun, 3 Dec 2023 03:25:58 -0800 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41 via Frontend Transport; Sun, 3 Dec 2023 03:25:55 -0800 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , Ori Kam , Suanming Mou , Alex Vesker , , Subject: [PATCH v1 03/23] net/mlx5/hws: fix tunnel protocol checks Date: Sun, 3 Dec 2023 13:25:23 +0200 Message-ID: <20231203112543.844014-4-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231203112543.844014-1-michaelba@nvidia.com> References: <20231203112543.844014-1-michaelba@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017098:EE_|CY5PR12MB6646:EE_ X-MS-Office365-Filtering-Correlation-Id: 1c87fe97-abb0-4c97-a496-08dbf3f2a6a2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: DrWa3rP2es0CKMTazpJdzyW3ydaAOT0afjp6dJahOMajOAnzRFtQ4q5s/ZZ0R+1X+lID2gu8HOhIjbiIlJZvGZnHOhjiEYw/5gzHnS5D7k1BMSAGII/pltnVDnIyEb/0fHQ4R/EU9mZjX1MieS6RXU4RaNMx6vVPxBfrQ8/lZ/X2m6XdIw7rrgmG4f2VE7GbSXoqlrF8mU+UPlze7Q7FAuwPnFlAzY8uIC5AnWkZ63j0Dg7b82yp6fKN/ZTWlAlh3dBLy+hiGdHAEqCs1VMlRovuCFPMXEs8fT20JlSXPp3SFskH74vibti6PmD3ELQzxQ4Cf3HpxYMx3b5jDjtkC3Dz2d57+Op+hLVn83uCZz4aQcup3dX80luoVdqyrFbw5maWF15/a2nNt37MfJnw97hsGuKV2VhEeb5T2DUbNQYe16dUaZWtPbG7BVpOqTsF2cEYU0y14L4y5NET2l15uL9jhoCqsD66vXShuX1pGtSYbNd4PEAwOOp/wFoftJZye+IP6+27zGICVlFE4uUrpGHpzcoXws8ZYGFqaPAoKMfRc9qfrrAS81v5TazX2ePYUPjSNNUZxcXy5Pmp4qnOv5U7f+4j8oN0DnvoBQe/tsRYNh7IycIYktj0Toj3FpMBbZMcxkDmrKVljduLe3e0/dysdCP38CB1FX1T7wFA1RslRTqtN4urkvREScwMFc7k+FOXe5YG2hY7/kyquAfit0gIwAKwrHaTnRHu7hXjFrpzafzJ4p5fAtkPRIWYl1jtPKTXCkzRSOOlmFllvuDb0w== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230031)(4636009)(39860400002)(396003)(136003)(346002)(376002)(230922051799003)(186009)(451199024)(82310400011)(1800799012)(64100799003)(46966006)(36840700001)(40470700004)(40460700003)(450100002)(54906003)(6916009)(316002)(86362001)(8936002)(8676002)(4326008)(70586007)(478600001)(70206006)(41300700001)(36756003)(5660300002)(2906002)(36860700001)(356005)(7636003)(47076005)(2616005)(6286002)(26005)(1076003)(7696005)(6666004)(83380400001)(82740400003)(426003)(336012)(40480700001)(55016003)(309714004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Dec 2023 11:26:10.4962 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1c87fe97-abb0-4c97-a496-08dbf3f2a6a2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017098.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6646 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Alex Vesker Align GRE, GTPU and VXLAN tunnel protocols to fail in case the packet is already tunneled. Also use local defines for protocol UDP ports for better layering of mlx5dr API. Fixes: c55c2bf35333 ("net/mlx5/hws: add definer layer") Fixes: 5bf14a4beb1a ("net/mlx5/hws: support matching on MPLSoUDP") Cc: valex@nvidia.com Cc: erezsh@nvidia.com Cc: stable@dpdk.org Signed-off-by: Alex Vesker --- drivers/net/mlx5/hws/mlx5dr_definer.c | 39 +++++++++++++-------------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index 0b60479406..bab1869369 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -8,8 +8,9 @@ #define BAD_PORT 0xBAD #define ETH_TYPE_IPV4_VXLAN 0x0800 #define ETH_TYPE_IPV6_VXLAN 0x86DD -#define ETH_VXLAN_DEFAULT_PORT 4789 -#define IP_UDP_PORT_MPLS 6635 +#define UDP_GTPU_PORT 2152 +#define UDP_VXLAN_PORT 4789 +#define UDP_PORT_MPLS 6635 #define UDP_ROCEV2_PORT 4791 #define DR_FLOW_LAYER_TUNNEL_NO_MPLS (MLX5_FLOW_LAYER_TUNNEL & ~MLX5_FLOW_LAYER_MPLS) @@ -158,7 +159,7 @@ struct mlx5dr_definer_conv_data { X(SET, tcp_protocol, STE_TCP, rte_flow_item_tcp) \ X(SET_BE16, tcp_src_port, v->hdr.src_port, rte_flow_item_tcp) \ X(SET_BE16, tcp_dst_port, v->hdr.dst_port, rte_flow_item_tcp) \ - X(SET, gtp_udp_port, RTE_GTPU_UDP_PORT, rte_flow_item_gtp) \ + X(SET, gtp_udp_port, UDP_GTPU_PORT, rte_flow_item_gtp) \ X(SET_BE32, gtp_teid, v->hdr.teid, rte_flow_item_gtp) \ X(SET, gtp_msg_type, v->hdr.msg_type, rte_flow_item_gtp) \ X(SET, gtp_ext_flag, !!v->hdr.gtp_hdr_info, rte_flow_item_gtp) \ @@ -166,8 +167,8 @@ struct mlx5dr_definer_conv_data { X(SET, gtp_ext_hdr_pdu, v->hdr.type, rte_flow_item_gtp_psc) \ X(SET, gtp_ext_hdr_qfi, v->hdr.qfi, rte_flow_item_gtp_psc) \ X(SET, vxlan_flags, v->flags, rte_flow_item_vxlan) \ - X(SET, vxlan_udp_port, ETH_VXLAN_DEFAULT_PORT, rte_flow_item_vxlan) \ - X(SET, mpls_udp_port, IP_UDP_PORT_MPLS, rte_flow_item_mpls) \ + X(SET, vxlan_udp_port, UDP_VXLAN_PORT, rte_flow_item_vxlan) \ + X(SET, mpls_udp_port, UDP_PORT_MPLS, rte_flow_item_mpls) \ X(SET, source_qp, v->queue, mlx5_rte_flow_item_sq) \ X(SET, tag, v->data, rte_flow_item_tag) \ X(SET, metadata, v->data, rte_flow_item_meta) \ @@ -1170,6 +1171,12 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, const struct rte_flow_item_gtp *m = item->mask; struct mlx5dr_definer_fc *fc; + if (cd->tunnel) { + DR_LOG(ERR, "Inner GTPU item not supported"); + rte_errno = ENOTSUP; + return rte_errno; + } + /* Overwrite GTPU dest port if not present */ fc = &cd->fc[DR_CALC_FNAME(L4_DPORT, false)]; if (!fc->tag_set && !cd->relaxed) { @@ -1344,9 +1351,13 @@ mlx5dr_definer_conv_item_vxlan(struct mlx5dr_definer_conv_data *cd, struct mlx5dr_definer_fc *fc; bool inner = cd->tunnel; - /* In order to match on VXLAN we must match on ether_type, ip_protocol - * and l4_dport. - */ + if (inner) { + DR_LOG(ERR, "Inner VXLAN item not supported"); + rte_errno = ENOTSUP; + return rte_errno; + } + + /* In order to match on VXLAN we must match on ip_protocol and l4_dport */ if (!cd->relaxed) { fc = &cd->fc[DR_CALC_FNAME(IP_PROTOCOL, inner)]; if (!fc->tag_set) { @@ -1369,12 +1380,6 @@ mlx5dr_definer_conv_item_vxlan(struct mlx5dr_definer_conv_data *cd, return 0; if (m->flags) { - if (inner) { - DR_LOG(ERR, "Inner VXLAN flags item not supported"); - rte_errno = ENOTSUP; - return rte_errno; - } - fc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_FLAGS]; fc->item_idx = item_idx; fc->tag_set = &mlx5dr_definer_vxlan_flags_set; @@ -1384,12 +1389,6 @@ mlx5dr_definer_conv_item_vxlan(struct mlx5dr_definer_conv_data *cd, } if (!is_mem_zero(m->vni, 3)) { - if (inner) { - DR_LOG(ERR, "Inner VXLAN vni item not supported"); - rte_errno = ENOTSUP; - return rte_errno; - } - fc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_VNI]; fc->item_idx = item_idx; fc->tag_set = &mlx5dr_definer_vxlan_vni_set;