From patchwork Thu Dec 14 14:50:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satheesh Paul Antonysamy X-Patchwork-Id: 135205 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C8670436F0; Thu, 14 Dec 2023 15:50:40 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 752F9432F0; Thu, 14 Dec 2023 15:50:34 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 88EEA432EE for ; Thu, 14 Dec 2023 15:50:32 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BE9LUmX002210 for ; Thu, 14 Dec 2023 06:50:31 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=zPkXK4RtopGIhgtZzEZBLItU9m5tJO5t18MtIvsZtAw=; b=JwW fpmK7Odipq8pyaBnda79ftJDyNY3rZuORGweAIULw2uIeB1FwapqFrZjsellrPA2 Xd0mrEe9kCJDA+5kg0cwvpklBzEvJSzEcPMNV3wBZgsX/scE1ootm/p2yJtSddHc l2AyiWMHg0Nm3ed+ma2z4QKHa5Cu3qbe536L2ltVgSsSv+ztvC/iPyEJIa12KmI7 cuz/Hk7NENG99aI9Q7HInA5XbmRnpCeysGSTnUGOoVYJVzGB7Gik+57I1ABYIRgx 9L8ZcW4UuUZ/xqXSeLvzIKGVjPl9WQ7CWvHGkx3ylumvXPROEfFoxDtfivhbpz+g AutK0mRkibFuaR1uEOQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3uyy0m921h-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 14 Dec 2023 06:50:31 -0800 (PST) Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 14 Dec 2023 06:50:30 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 14 Dec 2023 06:50:29 -0800 Received: from satheeshpaullabpc.. (unknown [10.28.34.33]) by maili.marvell.com (Postfix) with ESMTP id E43DE3F70A9; Thu, 14 Dec 2023 06:50:27 -0800 (PST) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Satheesh Paul Subject: [dpdk-dev] [PATCH v2 3/3] common/cnxk: add egress mirror support Date: Thu, 14 Dec 2023 20:20:16 +0530 Message-ID: <20231214145016.571806-3-psatheesh@marvell.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231214145016.571806-1-psatheesh@marvell.com> References: <20231214105813.570597-1-psatheesh@marvell.com> <20231214145016.571806-1-psatheesh@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: _6axzYpZTTCuQQVDEvD9NkX2Xlv-RMSO X-Proofpoint-ORIG-GUID: _6axzYpZTTCuQQVDEvD9NkX2Xlv-RMSO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Satha Rao Added ROC api to send packets on multiple links when egress mirror enabled. Signed-off-by: Satha Rao Reviewed-by: Nithin Dabilpuram Reviewed-by: Kiran Kumar K Reviewed-by: Satheesh Paul --- drivers/common/cnxk/roc_nix.h | 2 + drivers/common/cnxk/roc_nix_tm_ops.c | 70 ++++++++++++++++++++++++++++ drivers/common/cnxk/roc_npc.c | 26 +++++++++++ drivers/common/cnxk/version.map | 1 + 4 files changed, 99 insertions(+) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index c1ebf971f7..84e6fc3df5 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -755,6 +755,8 @@ int __roc_api roc_nix_tm_mark_config(struct roc_nix *roc_nix, int mark_red); uint64_t __roc_api roc_nix_tm_mark_format_get(struct roc_nix *roc_nix, uint64_t *flags); +int __roc_api roc_nix_tm_egress_link_cfg_set(struct roc_nix *roc_nix, uint64_t dst_pf_func, + bool enable); /* Ingress Policer API */ int __roc_api roc_nix_bpf_timeunit_get(struct roc_nix *roc_nix, diff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c index 2c53472047..900b182c76 100644 --- a/drivers/common/cnxk/roc_nix_tm_ops.c +++ b/drivers/common/cnxk/roc_nix_tm_ops.c @@ -1316,3 +1316,73 @@ roc_nix_tm_root_has_sp(struct roc_nix *roc_nix) return false; return true; } + +static inline struct nix * +pf_func_to_nix_get(uint16_t pf_func) +{ + struct roc_nix *roc_nix_tmp = NULL; + struct roc_nix_list *nix_list; + + nix_list = roc_idev_nix_list_get(); + if (nix_list == NULL) + return NULL; + + /* Find the NIX of given pf_func */ + TAILQ_FOREACH(roc_nix_tmp, nix_list, next) { + struct nix *nix = roc_nix_to_nix_priv(roc_nix_tmp); + + if (nix->dev.pf_func == pf_func) + return nix; + } + + return NULL; +} + +int +roc_nix_tm_egress_link_cfg_set(struct roc_nix *roc_nix, uint64_t dst_pf_func, bool enable) +{ + struct nix *src_nix = roc_nix_to_nix_priv(roc_nix), *dst_nix; + struct mbox *mbox = (&src_nix->dev)->mbox; + struct nix_txschq_config *req = NULL; + struct nix_tm_node_list *list; + struct nix_tm_node *node; + int rc = 0, k; + + dst_nix = pf_func_to_nix_get(dst_pf_func); + if (!dst_nix) + return -EINVAL; + + if (dst_nix == src_nix) + return 0; + + list = nix_tm_node_list(src_nix, src_nix->tm_tree); + TAILQ_FOREACH(node, list, node) { + if (node->hw_lvl != src_nix->tm_link_cfg_lvl) + continue; + + if (!(node->flags & NIX_TM_NODE_HWRES)) + continue; + + /* Allocating TL3 request */ + req = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox)); + req->lvl = src_nix->tm_link_cfg_lvl; + k = 0; + + /* Enable PFC/pause on the identified TL3 */ + req->reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(node->hw_id, dst_nix->tx_link); + if (enable) + req->regval[k] |= BIT_ULL(12); + else + req->regval[k] &= ~(BIT_ULL(12)); + req->regval_mask[k] = ~(BIT_ULL(12)); + k++; + + req->num_regs = k; + rc = mbox_process(mbox); + mbox_put(mbox); + if (rc) + goto err; + } +err: + return rc; +} diff --git a/drivers/common/cnxk/roc_npc.c b/drivers/common/cnxk/roc_npc.c index 65f99549c9..9a0fe5f4e2 100644 --- a/drivers/common/cnxk/roc_npc.c +++ b/drivers/common/cnxk/roc_npc.c @@ -1595,6 +1595,21 @@ roc_npc_flow_create(struct roc_npc *roc_npc, const struct roc_npc_attr *attr, goto err_exit; } + /* If Egress mirror requested then enable TL3_TL2_LINK_CFG */ + if (flow->is_sampling_rule && (flow->nix_intf == NIX_INTF_TX)) { + if (flow->mcast_pf_funcs[0] == npc->pf_func) + rc = roc_nix_tm_egress_link_cfg_set(roc_npc->roc_nix, + flow->mcast_pf_funcs[1], true); + else + rc = roc_nix_tm_egress_link_cfg_set(roc_npc->roc_nix, + flow->mcast_pf_funcs[0], true); + if (rc) { + plt_err("Adding egress mirror failed"); + *errcode = rc; + goto err_exit; + } + } + rc = npc_rss_action_program(roc_npc, actions, flow); if (rc != 0) { *errcode = rc; @@ -1706,6 +1721,17 @@ roc_npc_flow_destroy(struct roc_npc *roc_npc, struct roc_npc_flow *flow) return rc; } + /* Disable egress mirror rule */ + if (flow->is_sampling_rule && (flow->nix_intf == NIX_INTF_TX)) { + if (flow->mcast_pf_funcs[0] == npc->pf_func) + rc = roc_nix_tm_egress_link_cfg_set(roc_npc->roc_nix, + flow->mcast_pf_funcs[1], false); + else + rc = roc_nix_tm_egress_link_cfg_set(roc_npc->roc_nix, + flow->mcast_pf_funcs[0], false); + if (rc) + plt_err("Failed to remove egress mirror rule"); + } if (flow->is_sampling_rule) roc_nix_mcast_list_free(npc->mbox, flow->mcast_grp_index); diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 1b531da36d..7b6afa63a9 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -355,6 +355,7 @@ INTERNAL { roc_nix_switch_hdr_set; roc_nix_eeprom_info_get; roc_nix_smq_flush; + roc_nix_tm_egress_link_cfg_set; roc_nix_tm_dump; roc_nix_tm_err_to_rte_err; roc_nix_tm_fini;