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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by MWH0EPF000989EB.mail.protection.outlook.com (10.167.241.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7113.14 via Frontend Transport; Mon, 18 Dec 2023 07:49:22 +0000 Received: from 7dbylenovo.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Mon, 18 Dec 2023 01:49:20 -0600 From: Sivaprasad Tummala To: , , , , , , , CC: , , Subject: [PATCH 4/6] examples/ipsec-secgw: fix lcore ID restriction Date: Mon, 18 Dec 2023 07:49:03 +0000 Message-ID: <20231218074905.42749-4-sivaprasad.tummala@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231218074905.42749-1-sivaprasad.tummala@amd.com> References: <20231218074905.42749-1-sivaprasad.tummala@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989EB:EE_|SJ0PR12MB5454:EE_ X-MS-Office365-Filtering-Correlation-Id: 9f0b4f98-804a-4b3e-ae03-08dbff9dd95c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2023 07:49:22.3016 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9f0b4f98-804a-4b3e-ae03-08dbff9dd95c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989EB.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5454 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Currently the config option allows lcore IDs up to 255, irrespective of RTE_MAX_LCORES and needs to be fixed. The patch allows config options based on DPDK config. Fixes: d299106e8e31 ("examples/ipsec-secgw: add IPsec sample application") Cc: sergio.gonzalez.monroy@intel.com Cc: stable@dpdk.org Signed-off-by: Sivaprasad Tummala --- examples/ipsec-secgw/event_helper.h | 2 +- examples/ipsec-secgw/ipsec-secgw.c | 12 +++++++----- examples/ipsec-secgw/ipsec.c | 2 +- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/examples/ipsec-secgw/event_helper.h b/examples/ipsec-secgw/event_helper.h index dfb81bfcf1..9923700f03 100644 --- a/examples/ipsec-secgw/event_helper.h +++ b/examples/ipsec-secgw/event_helper.h @@ -102,7 +102,7 @@ struct eh_event_link_info { /**< Event port ID */ uint8_t eventq_id; /**< Event queue to be linked to the port */ - uint8_t lcore_id; + uint16_t lcore_id; /**< Lcore to be polling on this port */ }; diff --git a/examples/ipsec-secgw/ipsec-secgw.c b/examples/ipsec-secgw/ipsec-secgw.c index bf98d2618b..0c15ec5334 100644 --- a/examples/ipsec-secgw/ipsec-secgw.c +++ b/examples/ipsec-secgw/ipsec-secgw.c @@ -221,7 +221,7 @@ static const char *cfgfile; struct lcore_params { uint16_t port_id; uint8_t queue_id; - uint8_t lcore_id; + uint16_t lcore_id; } __rte_cache_aligned; static struct lcore_params lcore_params_array[MAX_LCORE_PARAMS]; @@ -810,7 +810,7 @@ check_flow_params(uint16_t fdir_portid, uint8_t fdir_qid) static int32_t check_poll_mode_params(struct eh_conf *eh_conf) { - uint8_t lcore; + uint16_t lcore; uint16_t portid; uint16_t i; int32_t socket_id; @@ -870,7 +870,7 @@ static int32_t init_lcore_rx_queues(void) { uint16_t i, nb_rx_queue; - uint8_t lcore; + uint16_t lcore; for (i = 0; i < nb_lcore_params; ++i) { lcore = lcore_params[i].lcore_id; @@ -1051,6 +1051,8 @@ parse_config(const char *q_arg) char *str_fld[_NUM_FLD]; int32_t i; uint32_t size; + unsigned int max_fld[_NUM_FLD] = {RTE_MAX_ETHPORTS, + 255, RTE_MAX_LCORE}; nb_lcore_params = 0; @@ -1071,7 +1073,7 @@ parse_config(const char *q_arg) for (i = 0; i < _NUM_FLD; i++) { errno = 0; int_fld[i] = strtoul(str_fld[i], &end, 0); - if (errno != 0 || end == str_fld[i] || int_fld[i] > 255) + if (errno != 0 || end == str_fld[i] || int_fld[i] > max_fld[i]) return -1; } if (nb_lcore_params >= MAX_LCORE_PARAMS) { @@ -1084,7 +1086,7 @@ parse_config(const char *q_arg) lcore_params_array[nb_lcore_params].queue_id = (uint8_t)int_fld[FLD_QUEUE]; lcore_params_array[nb_lcore_params].lcore_id = - (uint8_t)int_fld[FLD_LCORE]; + (uint16_t)int_fld[FLD_LCORE]; ++nb_lcore_params; } lcore_params = lcore_params_array; diff --git a/examples/ipsec-secgw/ipsec.c b/examples/ipsec-secgw/ipsec.c index f5cec4a928..5ebb71bb9a 100644 --- a/examples/ipsec-secgw/ipsec.c +++ b/examples/ipsec-secgw/ipsec.c @@ -259,7 +259,7 @@ create_lookaside_session(struct ipsec_ctx *ipsec_ctx_lcore[], continue; /* Looking for cryptodev, which can handle this SA */ - key.lcore_id = (uint8_t)lcore_id; + key.lcore_id = (uint16_t)lcore_id; key.cipher_algo = (uint8_t)sa->cipher_algo; key.auth_algo = (uint8_t)sa->auth_algo; key.aead_algo = (uint8_t)sa->aead_algo;