From patchwork Thu Jan 11 07:00:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Li X-Patchwork-Id: 135842 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 63C4D4388E; Thu, 11 Jan 2024 08:01:59 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1769740A6D; Thu, 11 Jan 2024 08:01:44 +0100 (CET) Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2069.outbound.protection.outlook.com [40.107.93.69]) by mails.dpdk.org (Postfix) with ESMTP id E34F3406BA for ; Thu, 11 Jan 2024 08:01:42 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ZmZywgPYoswUQ9Z+GHYtWEn52n3+Tg3hXBtEVJwc6JzGzCnEAkIccxgELnC2Ghcsb1hB9qTPBCBFYnvEhlQHuLJBPcmRAJ3uyqS21Da/kpMMmFhiGFxvdjeaVe0LMP8SbZwCAFfDdI7nuHWmq4wDgLajvAdjEHPb+bpe9vAUZTGRE/awxR1WsxjFPBVEJDwaXlvkjG4VYCSePrx9y1kHXwqzx2igK/G+mzDRe4PD4hnSs9tyTp9xY/xLYUNANTp8Jbp53AF61wJaYthkIXXB5HEYdQjwvmH6wk3XbTna7VmJ3N4lz87RqMHnkfs+DiOgKERghuSdbxtW4HIwICa5Cg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=dzoQXYF+YSsnR7uwtZrr3CJrsWfP2K68Zw+835E3qLE=; b=LHNISLQe9o78QYZ6WdTfLHjtXuQF8t008+p49z2qisxeSS4l280Vmm2eUFAieF+e7JnHe38pOgHow/wzAcTuR+Wpsmu0goIs2GTP87pDK8JswRrjWxkMNwOCk6QOxNzsB/M68ONiUN/7mw4Jxa5HJANRex+1L3omTYyoij+7oZK95RKFxUztWMJ7cS0kaDIPmEZTXGaGaM2KEzt1TNdAW2qDTRNzFfthssvD8rwaZMGmhHiKFLK14lJwJDYZRVQbWs2nmxP5E1bdNFk7VyUns+Em675LzocG6XLINoGhgT+W/w4t80JfNvJlXXEznxFYaLGLi2yJmPKRsr4AIJKwiA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=dzoQXYF+YSsnR7uwtZrr3CJrsWfP2K68Zw+835E3qLE=; b=Aq1CtxGhMmlBeivl5V5p5TnqRq8aW/pnWbXgYY88Egpw9/zZ4pWrUj4Sfg+53shI1ruwdQXlZi10JueKfgYe5VK3dbAFxVL5DOkVTMl0svC91iY1Jwka2OwzJExvDbb/qFozM9s2c20Hbe7HOoIwrSEqgTWl3PsrozMKu7+aweRLTQYyYqBmpMhq2iWOxayVBcOamGI2/vrkYLCVjuI1VHhGMAC7ME7hUVBZgel6nHZi7ndFsxxUoYWwbKbFOjsQO7DRHc0rKtk2AYWdCE7rUJ2F7Tm4LRLH1XGbcUbExACXtpkF4tfboOODyCQ5CaKn+f/NaRJBhqU2U75uQDd3ag== Received: from MW3PR05CA0010.namprd05.prod.outlook.com (2603:10b6:303:2b::15) by CH0PR12MB5387.namprd12.prod.outlook.com (2603:10b6:610:d6::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7181.18; Thu, 11 Jan 2024 07:01:40 +0000 Received: from MWH0EPF000989EC.namprd02.prod.outlook.com (2603:10b6:303:2b:cafe::b6) by MW3PR05CA0010.outlook.office365.com (2603:10b6:303:2b::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7202.12 via Frontend Transport; Thu, 11 Jan 2024 07:01:40 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by MWH0EPF000989EC.mail.protection.outlook.com (10.167.241.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7181.14 via Frontend Transport; Thu, 11 Jan 2024 07:01:39 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Wed, 10 Jan 2024 23:01:21 -0800 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Wed, 10 Jan 2024 23:01:17 -0800 From: Gavin Li To: , , , , , , , , CC: , , Itamar Gozlan Subject: [RFC 5/5] net/mlx5/hws: support VXLAN-GPE matching Date: Thu, 11 Jan 2024 09:00:43 +0200 Message-ID: <20240111070043.1276161-6-gavinl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111070043.1276161-1-gavinl@nvidia.com> References: <20240111070043.1276161-1-gavinl@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989EC:EE_|CH0PR12MB5387:EE_ X-MS-Office365-Filtering-Correlation-Id: 2ef23e59-dd94-46f4-3663-08dc127328fb X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rdwB4Bnl6z5Y32r7AvcbjK9uO1Y+HV+tR3Dag78pvunh8lCJzoQfVjmrScCBtQ3mYoaacXGEAPVl8MorbozJBMaR8WO+vsq4K2/VUU9igrTOWEg0PBJiQXNQoepCRnW22Ov4VzZZV+Qm3epP3AvBcmo2GICaocQE9ic09IyPeK967Fw6irwl+Rfj4K/yxMnzmv0rfLhB6V8hJaqTZ+wRK9RESArkyfvxHox9AOuMJfTC2lQHUxNJVt5Jk3Q2FHUkyZGbHyA3MOOcrxZNhWOPZVlK/p00HARnPNhphQnPE8nOp4bkUVWBeh0TvsP28VhBfybLz36ga+A/SY3unxnX2sFUu5nc79mRrW0k88DehovDhfOh8pdp+erk947P5GQzsfVN7MgC4IungP0x8O1GyGQrOjmHQawdlJ2RZM/21KMlUrF9qYU6kgfcieAGYmDeEtCpJ22f3o0TP0Q97ep06qrpBSuHWYKRiT/TwSx3GdEj5PX3lgYz70pV+UzjnehwWEJAzTJ1XJptCLtNWwfhgaqxMCgNNf/DTNiT9uW3oE6KR5lI7nwlbMTWR1malO/meRsskUYNvto+iNvWz2dAmd60wqFLpHnuwZM+C9PlOM1nZ6yArTtFWZ2zcVC3BSD6oh0fWvIDGShSsppu0JBh/LtaYQ+2kmhZUnGLAtIdd1tU2+4VCUA5IA5cREDl7YOtVY0srTx1TRkM7kpHekApIl1bgdLKXfAE7zkPbCHutYA1LSrtPb5axwoUcXFeNGoY X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230031)(4636009)(39860400002)(346002)(136003)(376002)(396003)(230922051799003)(1800799012)(451199024)(82310400011)(64100799003)(186009)(46966006)(40470700004)(36840700001)(40460700003)(40480700001)(55016003)(47076005)(110136005)(86362001)(36756003)(7636003)(356005)(36860700001)(82740400003)(8676002)(4326008)(83380400001)(2616005)(26005)(1076003)(107886003)(426003)(16526019)(336012)(6286002)(6666004)(7696005)(70206006)(54906003)(316002)(70586007)(6636002)(478600001)(5660300002)(41300700001)(2906002)(8936002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jan 2024 07:01:39.6452 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2ef23e59-dd94-46f4-3663-08dc127328fb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989EC.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5387 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for matching VXLAN-GPE tunnel header. Signed-off-by: Gavin Li Reviewed-by: Itamar Gozlan Reviewed-by: Dariusz Sosnowski --- doc/guides/rel_notes/release_24_03.rst | 6 ++ drivers/net/mlx5/hws/mlx5dr_definer.c | 117 +++++++++++++++++++++++++ drivers/net/mlx5/hws/mlx5dr_definer.h | 13 +++ drivers/net/mlx5/mlx5_flow_hw.c | 1 + 4 files changed, 137 insertions(+) diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst index 2c0e2930cc..d5e1b1ad37 100644 --- a/doc/guides/rel_notes/release_24_03.rst +++ b/doc/guides/rel_notes/release_24_03.rst @@ -59,6 +59,12 @@ New Features * Added support for accumulating from src field to dst field. + * Added support for VXLAN-GPE flags/rsvd0/rsvd fields matching in DV flow + engine (``dv_flow_en`` = 1). + + * Added support for VXLAN-GPE matching in HW Steering flow engine + (``dv_flow_en`` = 2). + Removed Items ------------- diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index 0b60479406..8958049c8f 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -9,6 +9,7 @@ #define ETH_TYPE_IPV4_VXLAN 0x0800 #define ETH_TYPE_IPV6_VXLAN 0x86DD #define ETH_VXLAN_DEFAULT_PORT 4789 +#define ETH_VXLAN_GPE_DEFAULT_PORT 4790 #define IP_UDP_PORT_MPLS 6635 #define UDP_ROCEV2_PORT 4791 #define DR_FLOW_LAYER_TUNNEL_NO_MPLS (MLX5_FLOW_LAYER_TUNNEL & ~MLX5_FLOW_LAYER_MPLS) @@ -167,6 +168,10 @@ struct mlx5dr_definer_conv_data { X(SET, gtp_ext_hdr_qfi, v->hdr.qfi, rte_flow_item_gtp_psc) \ X(SET, vxlan_flags, v->flags, rte_flow_item_vxlan) \ X(SET, vxlan_udp_port, ETH_VXLAN_DEFAULT_PORT, rte_flow_item_vxlan) \ + X(SET, vxlan_gpe_udp_port, ETH_VXLAN_GPE_DEFAULT_PORT, rte_flow_item_vxlan_gpe) \ + X(SET, vxlan_gpe_flags, v->flags, rte_flow_item_vxlan_gpe) \ + X(SET, vxlan_gpe_protocol, v->protocol, rte_flow_item_vxlan_gpe) \ + X(SET, vxlan_gpe_rsvd1, v->rsvd1, rte_flow_item_vxlan_gpe) \ X(SET, mpls_udp_port, IP_UDP_PORT_MPLS, rte_flow_item_mpls) \ X(SET, source_qp, v->queue, mlx5_rte_flow_item_sq) \ X(SET, tag, v->data, rte_flow_item_tag) \ @@ -691,6 +696,28 @@ mlx5dr_definer_ib_l4_qp_set(struct mlx5dr_definer_fc *fc, memcpy(tag + fc->byte_off, &v->hdr.dst_qp, sizeof(v->hdr.dst_qp)); } +static void +mlx5dr_definer_vxlan_gpe_vni_set(struct mlx5dr_definer_fc *fc, + const void *item_spec, + uint8_t *tag) +{ + const struct rte_flow_item_vxlan_gpe *v = item_spec; + + memcpy(tag + fc->byte_off, v->vni, sizeof(v->vni)); +} + +static void +mlx5dr_definer_vxlan_gpe_rsvd0_set(struct mlx5dr_definer_fc *fc, + const void *item_spec, + uint8_t *tag) +{ + const struct rte_flow_item_vxlan_gpe *v = item_spec; + uint16_t rsvd0; + + rsvd0 = (v->rsvd0[0] << 8 | v->rsvd0[1]); + DR_SET(tag, rsvd0, fc->byte_off, fc->bit_off, fc->bit_mask); +} + static int mlx5dr_definer_conv_item_eth(struct mlx5dr_definer_conv_data *cd, struct rte_flow_item *item, @@ -2385,6 +2412,92 @@ mlx5dr_definer_conv_item_ib_l4(struct mlx5dr_definer_conv_data *cd, return 0; } +static int +mlx5dr_definer_conv_item_vxlan_gpe(struct mlx5dr_definer_conv_data *cd, + struct rte_flow_item *item, + int item_idx) +{ + const struct rte_flow_item_vxlan_gpe *m = item->mask; + struct mlx5dr_definer_fc *fc; + bool inner = cd->tunnel; + + if (inner) { + DR_LOG(ERR, "Inner VXLAN GPE item not supported"); + rte_errno = ENOTSUP; + return rte_errno; + } + + /* In order to match on VXLAN GPE we must match on ip_protocol and l4_dport */ + if (!cd->relaxed) { + fc = &cd->fc[DR_CALC_FNAME(IP_PROTOCOL, inner)]; + if (!fc->tag_set) { + fc->item_idx = item_idx; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + fc->tag_set = &mlx5dr_definer_udp_protocol_set; + DR_CALC_SET(fc, eth_l2, l4_type_bwc, inner); + } + + fc = &cd->fc[DR_CALC_FNAME(L4_DPORT, inner)]; + if (!fc->tag_set) { + fc->item_idx = item_idx; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + fc->tag_set = &mlx5dr_definer_vxlan_gpe_udp_port_set; + DR_CALC_SET(fc, eth_l4, destination_port, inner); + } + } + + if (!m) + return 0; + + if (m->flags) { + fc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_GPE_FLAGS]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_vxlan_gpe_flags_set; + DR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_0); + fc->bit_mask = __mlx5_mask(header_vxlan_gpe, flags); + fc->bit_off = __mlx5_dw_bit_off(header_vxlan_gpe, flags); + } + + if (!is_mem_zero(m->rsvd0, 2)) { + fc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_GPE_RSVD0]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_vxlan_gpe_rsvd0_set; + DR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_0); + fc->bit_mask = __mlx5_mask(header_vxlan_gpe, rsvd0); + fc->bit_off = __mlx5_dw_bit_off(header_vxlan_gpe, rsvd0); + } + + if (m->protocol) { + fc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_GPE_PROTO]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_vxlan_gpe_protocol_set; + DR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_0); + fc->byte_off += MLX5_BYTE_OFF(header_vxlan_gpe, protocol); + fc->bit_mask = __mlx5_mask(header_vxlan_gpe, protocol); + fc->bit_off = __mlx5_dw_bit_off(header_vxlan_gpe, protocol); + } + + if (!is_mem_zero(m->vni, 3)) { + fc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_GPE_VNI]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_vxlan_gpe_vni_set; + DR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_1); + fc->bit_mask = __mlx5_mask(header_vxlan_gpe, vni); + fc->bit_off = __mlx5_dw_bit_off(header_vxlan_gpe, vni); + } + + if (m->rsvd1) { + fc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_GPE_RSVD1]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_vxlan_gpe_rsvd1_set; + DR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_1); + fc->bit_mask = __mlx5_mask(header_vxlan_gpe, rsvd1); + fc->bit_off = __mlx5_dw_bit_off(header_vxlan_gpe, rsvd1); + } + + return 0; +} + static int mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, struct mlx5dr_match_template *mt, @@ -2537,6 +2650,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, ret = mlx5dr_definer_conv_item_ptype(&cd, items, i); item_flags |= MLX5_FLOW_ITEM_PTYPE; break; + case RTE_FLOW_ITEM_TYPE_VXLAN_GPE: + ret = mlx5dr_definer_conv_item_vxlan_gpe(&cd, items, i); + item_flags |= MLX5_FLOW_LAYER_VXLAN_GPE; + break; default: DR_LOG(ERR, "Unsupported item type %d", items->type); rte_errno = ENOTSUP; diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h index 6f1c99e37a..3dc5f4438d 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.h +++ b/drivers/net/mlx5/hws/mlx5dr_definer.h @@ -91,6 +91,11 @@ enum mlx5dr_definer_fname { MLX5DR_DEFINER_FNAME_VPORT_REG_C_0, MLX5DR_DEFINER_FNAME_VXLAN_FLAGS, MLX5DR_DEFINER_FNAME_VXLAN_VNI, + MLX5DR_DEFINER_FNAME_VXLAN_GPE_FLAGS, + MLX5DR_DEFINER_FNAME_VXLAN_GPE_RSVD0, + MLX5DR_DEFINER_FNAME_VXLAN_GPE_PROTO, + MLX5DR_DEFINER_FNAME_VXLAN_GPE_VNI, + MLX5DR_DEFINER_FNAME_VXLAN_GPE_RSVD1, MLX5DR_DEFINER_FNAME_SOURCE_QP, MLX5DR_DEFINER_FNAME_REG_0, MLX5DR_DEFINER_FNAME_REG_1, @@ -593,6 +598,14 @@ struct mlx5_ifc_header_vxlan_bits { u8 reserved2[0x8]; }; +struct mlx5_ifc_header_vxlan_gpe_bits { + u8 flags[0x8]; + u8 rsvd0[0x10]; + u8 protocol[0x8]; + u8 vni[0x18]; + u8 rsvd1[0x8]; +}; + struct mlx5_ifc_header_gre_bits { union { u8 c_rsvd0_ver[0x10]; diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index c4a90a3690..6d8f4f8f8b 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -6827,6 +6827,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev, case RTE_FLOW_ITEM_TYPE_GTP: case RTE_FLOW_ITEM_TYPE_GTP_PSC: case RTE_FLOW_ITEM_TYPE_VXLAN: + case RTE_FLOW_ITEM_TYPE_VXLAN_GPE: case RTE_FLOW_ITEM_TYPE_MPLS: case MLX5_RTE_FLOW_ITEM_TYPE_SQ: case RTE_FLOW_ITEM_TYPE_GRE: