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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jan 2024 08:03:10.9007 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ebdfea4a-045b-43d6-7887-08dc1344eb8b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6907 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This adds matching on the reserved fields of VXLAN-GPE header (the 16-bits before Next Protocol and the last 8-bits). To support all the header fields, tunnel_header_0_1 should be supported by FW and misc5_cap is set. If one of the reserved fields is matched on, misc5 is used for matching. Otherwise, keep using misc3 Signed-off-by: Gavin Li Acked-by: Dariusz Sosnowski --- doc/guides/nics/mlx5.rst | 5 +++++ drivers/net/mlx5/mlx5_flow.c | 5 +++++ drivers/net/mlx5/mlx5_flow_dv.c | 32 ++++++++++++++++++++++++++------ 3 files changed, 36 insertions(+), 6 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 7bfd6c6aeb..27384d5a86 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -311,6 +311,11 @@ Limitations Group zero's behavior may differ which depends on FW. Matching value equals 0 (value & mask) is not supported. +- Matching on VXLAN-GPE header fields: + + - ``rsvd0``/``rsvd1`` matching support depends on FW version when using DV flow + engine (``dv_flow_en`` = 1). + - L3 VXLAN and VXLAN-GPE tunnels cannot be supported together with MPLSoGRE and MPLSoUDP. - MPLSoGRE is not supported in HW steering (``dv_flow_en`` = 2). diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index ffa183dc1b..9b6f483d3f 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -3316,6 +3316,11 @@ mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, "no outer UDP layer found"); if (!mask) mask = &rte_flow_item_vxlan_gpe_mask; + if (priv->sh->misc5_cap && priv->sh->tunnel_header_0_1) { + nic_mask.rsvd0[0] = 0xff; + nic_mask.rsvd0[1] = 0xff; + nic_mask.rsvd1 = 0xff; + } ret = mlx5_flow_item_acceptable (item, (const uint8_t *)mask, (const uint8_t *)&nic_mask, diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 97f55003c3..f3589da654 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -9813,14 +9813,10 @@ flow_dv_translate_item_vxlan_gpe(void *key, const struct rte_flow_item *item, vxlan_v = vxlan_m; else if (key_type == MLX5_SET_MATCHER_HS_V) vxlan_m = vxlan_v; - for (i = 0; i < size; ++i) - vni_v[i] = vxlan_m->hdr.vni[i] & vxlan_v->hdr.vni[i]; if (vxlan_m->hdr.flags) { flags_m = vxlan_m->hdr.flags; flags_v = vxlan_v->hdr.flags; } - MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, - flags_m & flags_v); m_protocol = vxlan_m->hdr.protocol; v_protocol = vxlan_v->hdr.protocol; if (!m_protocol) { @@ -9839,8 +9835,32 @@ flow_dv_translate_item_vxlan_gpe(void *key, const struct rte_flow_item *item, if (key_type & MLX5_SET_MATCHER_M) v_protocol = m_protocol; } - MLX5_SET(fte_match_set_misc3, misc_v, - outer_vxlan_gpe_next_protocol, m_protocol & v_protocol); + /* + * If only match flags/protocol/vni field, keep using misc3 for matching. + * If need to match rsvd0 or rsvd1, using misc5 and do not need using misc3. + */ + if (!(vxlan_m->hdr.rsvd0[0] || vxlan_m->hdr.rsvd0[1] || vxlan_m->hdr.rsvd1)) { + for (i = 0; i < size; ++i) + vni_v[i] = vxlan_m->hdr.vni[i] & vxlan_v->hdr.vni[i]; + MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, + flags_m & flags_v); + MLX5_SET(fte_match_set_misc3, misc_v, + outer_vxlan_gpe_next_protocol, m_protocol & v_protocol); + } else { + uint32_t tunnel_v; + void *misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5); + + tunnel_v = (flags_m & flags_v) << 24 | + (vxlan_v->hdr.rsvd0[0] & vxlan_m->hdr.rsvd0[0]) << 16 | + (vxlan_v->hdr.rsvd0[1] & vxlan_m->hdr.rsvd0[1]) << 8 | + (m_protocol & v_protocol); + MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_0, tunnel_v); + tunnel_v = (vxlan_v->hdr.vni[0] & vxlan_m->hdr.vni[0]) << 24 | + (vxlan_v->hdr.vni[1] & vxlan_m->hdr.vni[1]) << 16 | + (vxlan_v->hdr.vni[2] & vxlan_m->hdr.vni[2]) << 8 | + (vxlan_v->hdr.rsvd1 & vxlan_m->hdr.rsvd1); + MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_1, tunnel_v); + } } /**