From patchwork Tue Jan 23 11:40:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bruce Richardson X-Patchwork-Id: 136060 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AB2B4439A7; Tue, 23 Jan 2024 12:41:32 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0F0DF42D7B; Tue, 23 Jan 2024 12:41:21 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by mails.dpdk.org (Postfix) with ESMTP id 68A94410F1; Tue, 23 Jan 2024 12:41:17 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706010078; x=1737546078; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2faNGX1t60W20DDcoH4JIR86uc/p92HeEXCC+AhVIJI=; b=VnzvhzTnstSYXJxlbpuWt3boLHUWtv8TIs2eiPcig/yCkBkXBx/lr/SO OtZtVYArUtfW8QkRQPQtlsUpQ+UX+dRFVHPEhBVlNNvitLDJOnbu8Qqpj cDD8gMHucnz7SS78RktfOI8iH49Z3LeoaWx05whoNC83ngg00/wmbtyk4 WJtzmesXBvlPYe51y+4CIfHC3JCwly4dbxDpi/4TQ19AGoQb3Q3Mi5/7z 2ZujrbIyCrC4KQhhvTt8Q617AbXWERdKLQ7W3bu1zFeeAz86XOR1rJs9S GEi3G+g3s5Lgf6JJaPs+NwixDVrw+aXbWOu2eJDJkQGnZJRyYdX2Ba/cd Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10961"; a="22965770" X-IronPort-AV: E=Sophos;i="6.05,214,1701158400"; d="scan'208";a="22965770" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jan 2024 03:41:17 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,214,1701158400"; d="scan'208";a="27722331" Received: from silpixa00400957.ir.intel.com (HELO silpixa00401385.ir.intel.com) ([10.237.214.26]) by orviesa002.jf.intel.com with ESMTP; 23 Jan 2024 03:41:16 -0800 From: Bruce Richardson To: dev@dpdk.org Cc: Bruce Richardson , stable@dpdk.org Subject: [PATCH 3/6] net/iavf: remove incorrect 16B descriptor read block Date: Tue, 23 Jan 2024 11:40:50 +0000 Message-Id: <20240123114053.172189-4-bruce.richardson@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240123114053.172189-1-bruce.richardson@intel.com> References: <20240123114053.172189-1-bruce.richardson@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org By default, the driver works with 32B descriptors, but has a separate descriptor read block for reading two descriptors at a time when using 16B descriptors. However, the 32B reads used are not guaranteed to be atomic, which will cause issues if that is not the case on a system, since the descriptors may be read in an undefined order. Remove the block, to avoid issues, and just use the regular descriptor reading path for 16B descriptors, if that support is enabled at build time. Fixes: af0c246a3800 ("net/iavf: enable AVX2 for iavf") Cc: stable@dpdk.org Signed-off-by: Bruce Richardson --- drivers/net/iavf/iavf_rxtx_vec_avx2.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/drivers/net/iavf/iavf_rxtx_vec_avx2.c b/drivers/net/iavf/iavf_rxtx_vec_avx2.c index 510b4d8f1c..3cec1eef9d 100644 --- a/drivers/net/iavf/iavf_rxtx_vec_avx2.c +++ b/drivers/net/iavf/iavf_rxtx_vec_avx2.c @@ -194,19 +194,6 @@ _iavf_recv_raw_pkts_vec_avx2(struct iavf_rx_queue *rxq, #endif __m256i raw_desc0_1, raw_desc2_3, raw_desc4_5, raw_desc6_7; -#ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC - /* for AVX we need alignment otherwise loads are not atomic */ - if (avx_aligned) { - /* load in descriptors, 2 at a time, in reverse order */ - raw_desc6_7 = _mm256_load_si256((void *)(rxdp + 6)); - rte_compiler_barrier(); - raw_desc4_5 = _mm256_load_si256((void *)(rxdp + 4)); - rte_compiler_barrier(); - raw_desc2_3 = _mm256_load_si256((void *)(rxdp + 2)); - rte_compiler_barrier(); - raw_desc0_1 = _mm256_load_si256((void *)(rxdp + 0)); - } else -#endif { const __m128i raw_desc7 = _mm_load_si128((void *)(rxdp + 7));