From patchwork Tue Jan 23 16:54:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 136065 X-Patchwork-Delegate: maxime.coquelin@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3A100439A9; Tue, 23 Jan 2024 17:58:02 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4D360410F6; Tue, 23 Jan 2024 17:57:57 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) by mails.dpdk.org (Postfix) with ESMTP id 3E70D400D7; Tue, 23 Jan 2024 17:57:55 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706029074; x=1737565074; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Nh1TV9Od/mm/7OJmJ50Jid4Wq9Xj4wRy3bRyrXy0TMc=; b=FNW0RRfGf01omxcBNXmEBlCVLGKohSWT7dEjWFTAbC97AdXfFxZ4OY2L 6ygQxC06s91UUexXZWMyt763KmoSTqfcDFMMXXlmwNY0FtcgwAgBdQ7Sf DoYyxUKF+ntDzhCjddwqOsxS5Ds2zZHZklasvGUIUEZAXN/06bu75wlLj GdSutTg+JN0lCYy2B4mffyimpB6cTQrH0QWFcm4qcXXtLnfECch7w0Cxg OkMFnYg3iwpASrmN6/MYuxPgPGSx/A3AiMooo2y3rermFjHmCl0gUrsQ5 u0zcJrE2QpB9FP94WKL6VgeVx4WMRj/JLzjf6Z6YeYNjIWYzziHFj+QFd w==; X-IronPort-AV: E=McAfee;i="6600,9927,10962"; a="8336618" X-IronPort-AV: E=Sophos;i="6.05,214,1701158400"; d="scan'208";a="8336618" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jan 2024 08:57:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10962"; a="786116238" X-IronPort-AV: E=Sophos;i="6.05,214,1701158400"; d="scan'208";a="786116238" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga002.jf.intel.com with ESMTP; 23 Jan 2024 08:57:52 -0800 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v5 1/5] doc: fix fpga 5gnr configuration values Date: Tue, 23 Jan 2024 08:54:50 -0800 Message-Id: <20240123165454.104465-2-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20240123165454.104465-1-hernan.vargas@intel.com> References: <20240123165454.104465-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org flr_timeout was removed from the code a while ago, updating doc. Fix minor typo in 5GNR example. Fixes: 2d4306438c92 ("baseband/fpga_5gnr_fec: add configure function") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- doc/guides/bbdevs/fpga_5gnr_fec.rst | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/doc/guides/bbdevs/fpga_5gnr_fec.rst b/doc/guides/bbdevs/fpga_5gnr_fec.rst index 956dd6bed560..99fc936829a8 100644 --- a/doc/guides/bbdevs/fpga_5gnr_fec.rst +++ b/doc/guides/bbdevs/fpga_5gnr_fec.rst @@ -100,7 +100,6 @@ parameters defined in ``rte_fpga_5gnr_fec_conf`` structure: uint8_t dl_bandwidth; uint8_t ul_load_balance; uint8_t dl_load_balance; - uint16_t flr_time_out; }; - ``pf_mode_en``: identifies whether only PF is to be used, or the VFs. PF and @@ -126,10 +125,6 @@ parameters defined in ``rte_fpga_5gnr_fec_conf`` structure: If all hardware queues exceeds the watermark, no code blocks will be streamed in from UL/DL code block FIFO. -- ``flr_time_out``: specifies how many 16.384us to be FLR time out. The - time_out = flr_time_out x 16.384us. For instance, if you want to set 10ms for - the FLR time out then set this setting to 0x262=610. - An example configuration code calling the function ``rte_fpga_5gnr_fec_configure()`` is shown below: @@ -154,7 +149,7 @@ below: /* setup FPGA PF */ ret = rte_fpga_5gnr_fec_configure(info->dev_name, &conf); TEST_ASSERT_SUCCESS(ret, - "Failed to configure 4G FPGA PF for bbdev %s", + "Failed to configure 5GNR FPGA PF for bbdev %s", info->dev_name);