From patchwork Fri Feb 23 15:12:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ciara Power X-Patchwork-Id: 137106 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2FF4043B82; Fri, 23 Feb 2024 16:13:34 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A315442830; Fri, 23 Feb 2024 16:13:16 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) by mails.dpdk.org (Postfix) with ESMTP id 368D541143 for ; Fri, 23 Feb 2024 16:13:13 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1708701193; x=1740237193; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2aw1fmhojMAvynOxgezvpkUwIeOU0edo1jG/RdCdU5E=; b=RvOpLwwhudMnnhVc7P6SX+9lgY7EjNl5oiH8eg4vnnP/3ayTcVG+gv1I XnUJoibIVgBZR/YHfZ3V5R3kQFuYErTX6WXGfrjdzrgLo/5yPpfkwykqS Fz2dWd7m9Dhd70hdHs7oMPZtpG7JUGXb27wSnNSYpEFAfCgJSth9Oo/nu abR1PhPwF3X1T/3Cz8eBD+27pNAVFZ96jLGLiMJsCWcVNeL0CSA7xaxDn qwmicQG1k+WD3LYUYLSMHuKiIxjLIfNQq+qUqNJKuZdA6LX52pY3fgLn5 OIuUMUzIZGsllOprmmJFrGW8M526PyMqqxoWEtj+L8fMY7gH44aHovlQ3 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10993"; a="2905940" X-IronPort-AV: E=Sophos;i="6.06,180,1705392000"; d="scan'208";a="2905940" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Feb 2024 07:13:13 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,180,1705392000"; d="scan'208";a="5881556" Received: from silpixa00401797.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.113]) by fmviesa009.fm.intel.com with ESMTP; 23 Feb 2024 07:13:11 -0800 From: Ciara Power To: dev@dpdk.org Cc: gakhil@marvell.com, kai.ji@intel.com, arkadiuszx.kusztal@intel.com, Ciara Power Subject: [PATCH v2 3/4] common/qat: add new gen3 CMAC macros Date: Fri, 23 Feb 2024 15:12:54 +0000 Message-Id: <20240223151255.3310490-4-ciara.power@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223151255.3310490-1-ciara.power@intel.com> References: <20231219155124.4133385-1-ciara.power@intel.com> <20240223151255.3310490-1-ciara.power@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The new QAT GEN3 device uses new macros for CMAC values, rather than using XCBC_MAC ones. The wireless slice handles CMAC in the new gen3 device, and no key precomputes are required by SW. Signed-off-by: Ciara Power --- drivers/common/qat/qat_adf/icp_qat_hw.h | 4 +++- drivers/crypto/qat/qat_sym_session.c | 28 +++++++++++++++++++++---- 2 files changed, 27 insertions(+), 5 deletions(-) diff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h b/drivers/common/qat/qat_adf/icp_qat_hw.h index 4651fb90bb..b99dde2176 100644 --- a/drivers/common/qat/qat_adf/icp_qat_hw.h +++ b/drivers/common/qat/qat_adf/icp_qat_hw.h @@ -75,7 +75,7 @@ enum icp_qat_hw_auth_algo { ICP_QAT_HW_AUTH_ALGO_RESERVED = 20, ICP_QAT_HW_AUTH_ALGO_RESERVED1 = 21, ICP_QAT_HW_AUTH_ALGO_RESERVED2 = 22, - ICP_QAT_HW_AUTH_ALGO_RESERVED3 = 22, + ICP_QAT_HW_AUTH_ALGO_AES_128_CMAC = 22, ICP_QAT_HW_AUTH_ALGO_RESERVED4 = 23, ICP_QAT_HW_AUTH_ALGO_RESERVED5 = 24, ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_32 = 25, @@ -180,6 +180,7 @@ struct icp_qat_hw_auth_setup { #define ICP_QAT_HW_ZUC_256_MAC_32_STATE1_SZ 8 #define ICP_QAT_HW_ZUC_256_MAC_64_STATE1_SZ 8 #define ICP_QAT_HW_ZUC_256_MAC_128_STATE1_SZ 16 +#define ICP_QAT_HW_AES_CMAC_STATE1_SZ 16 #define ICP_QAT_HW_NULL_STATE2_SZ 32 #define ICP_QAT_HW_MD5_STATE2_SZ 16 @@ -208,6 +209,7 @@ struct icp_qat_hw_auth_setup { #define ICP_QAT_HW_GALOIS_H_SZ 16 #define ICP_QAT_HW_GALOIS_LEN_A_SZ 8 #define ICP_QAT_HW_GALOIS_E_CTR0_SZ 16 +#define ICP_QAT_HW_AES_128_CMAC_STATE2_SZ 16 struct icp_qat_hw_auth_sha512 { struct icp_qat_hw_auth_setup inner_setup; diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c index ebdad0bd67..b1649b8d18 100644 --- a/drivers/crypto/qat/qat_sym_session.c +++ b/drivers/crypto/qat/qat_sym_session.c @@ -922,11 +922,20 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev, session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC; break; case RTE_CRYPTO_AUTH_AES_CMAC: - session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC; session->aes_cmac = 1; - if (internals->qat_dev->has_wireless_slice) { - is_wireless = 1; - session->is_wireless = 1; + if (!internals->qat_dev->has_wireless_slice) { + session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC; + break; + } + is_wireless = 1; + session->is_wireless = 1; + switch (key_length) { + case ICP_QAT_HW_AES_128_KEY_SZ: + session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_128_CMAC; + break; + default: + QAT_LOG(ERR, "Invalid key length: %d", key_length); + return -ENOTSUP; } break; case RTE_CRYPTO_AUTH_AES_GMAC: @@ -1309,6 +1318,9 @@ static int qat_hash_get_state1_size(enum icp_qat_hw_auth_algo qat_hash_alg) case ICP_QAT_HW_AUTH_ALGO_NULL: return QAT_HW_ROUND_UP(ICP_QAT_HW_NULL_STATE1_SZ, QAT_HW_DEFAULT_ALIGNMENT); + case ICP_QAT_HW_AUTH_ALGO_AES_128_CMAC: + return QAT_HW_ROUND_UP(ICP_QAT_HW_AES_CMAC_STATE1_SZ, + QAT_HW_DEFAULT_ALIGNMENT); case ICP_QAT_HW_AUTH_ALGO_DELIMITER: /* return maximum state1 size in this case */ return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA512_STATE1_SZ, @@ -1345,6 +1357,7 @@ static int qat_hash_get_digest_size(enum icp_qat_hw_auth_algo qat_hash_alg) case ICP_QAT_HW_AUTH_ALGO_MD5: return ICP_QAT_HW_MD5_STATE1_SZ; case ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC: + case ICP_QAT_HW_AUTH_ALGO_AES_128_CMAC: return ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ; case ICP_QAT_HW_AUTH_ALGO_DELIMITER: /* return maximum digest size in this case */ @@ -2353,6 +2366,7 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc, || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_64 || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_128 || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC + || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_128_CMAC || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SM3 @@ -2593,6 +2607,12 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc, return -EFAULT; } break; + case ICP_QAT_HW_AUTH_ALGO_AES_128_CMAC: + state1_size = ICP_QAT_HW_AES_CMAC_STATE1_SZ; + memset(cdesc->cd_cur_ptr, 0, state1_size); + memcpy(cdesc->cd_cur_ptr + state1_size, authkey, authkeylen); + state2_size = ICP_QAT_HW_AES_128_CMAC_STATE2_SZ; + break; case ICP_QAT_HW_AUTH_ALGO_GALOIS_128: case ICP_QAT_HW_AUTH_ALGO_GALOIS_64: cdesc->qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_GCM;