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(seliicwb00002.seli.gic.ericsson.se [10.156.25.100]) by seliicinfr00049.seli.gic.ericsson.se (Postfix) with ESMTP id 957A8380061; Sun, 25 Feb 2024 16:11:53 +0100 (CET) From: =?utf-8?q?Mattias_R=C3=B6nnblom?= To: CC: , =?utf-8?q?Morten_Br=C3=B8rup?= , Stephen Hemminger , =?utf-8?q?Mattias_R=C3=B6nn?= =?utf-8?q?blom?= Subject: [RFC v4 3/6] random: keep PRNG state in lcore variable Date: Sun, 25 Feb 2024 16:03:27 +0100 Message-ID: <20240225150330.517225-4-mattias.ronnblom@ericsson.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240225150330.517225-1-mattias.ronnblom@ericsson.com> References: <20240220084908.488252-2-mattias.ronnblom@ericsson.com> <20240225150330.517225-1-mattias.ronnblom@ericsson.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU2PEPF0001E9C6:EE_|AS8PR07MB7560:EE_ X-MS-Office365-Filtering-Correlation-Id: 348d29aa-ed2c-44a3-0743-08dc36141ad8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: BdnUZwG51qYjJ41HCkPTqs6i8MIBc+aG9MqI7Z3WMDP6uCsv91H+f105amuvTZ/2DnQjugjX0GNSCWHeRkyO+/S2boYcEgLDs6MsSXLpUIYQqGe21Xv95eG00u7vq3hW3GCJMFzqUL55ibBDHGYh6igZZ/LByk6Tu+SvB8ajKUuDx0KHqSAmWRzMS/nUc1WBDg2YeaMA+RCtSzokIOKe6x4lb0hdCVbIr+JG7eRFfk1ahAx2iNpvcRPs38sLauybf94g549Spe/A5bMklCqo232W1xQWf+TLpt0LLIf3auo1J6SU8x2tZzv4yeZpo9AHW4iZLFpD0O63fLOAaC0iJHtBSzK8eTnmkYmWQb8f2L0ovgvk61heRXFqpZCf0Hwu1wShvCQwZga4PKmHvQos2LJrFdIy/xVsfP2ceDP3ejhrCJ66lsDc0G98by89qNqlrvUx8VRaM450MbPZv8yKbYXKdzvvZ7vmZV2vNIcOHkWbdJPYVFtzRXWLs3Y+Na93Jx7P2kBwxfkAiqUWQqmgMUKKLJ0tlyxVuXbe70ds88l4gQaCE4M9wMPHOlWjx/W9ElGq3QscmZsJKUZU7SI+HMJ70WiTXaOhA8UGqWjUEq0jfadRqrIXNtqyQOQxDTaPXfXg1xTwB221qX2xD/vZ7g== X-Forefront-Antispam-Report: CIP:192.176.1.74; CTRY:SE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:oa.msg.ericsson.com; PTR:office365.se.ericsson.net; CAT:NONE; SFS:(13230031)(36860700004)(46966006)(40470700004); DIR:OUT; SFP:1101; X-OriginatorOrg: ericsson.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Feb 2024 15:11:55.6441 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 348d29aa-ed2c-44a3-0743-08dc36141ad8 X-MS-Exchange-CrossTenant-Id: 92e84ceb-fbfd-47ab-be52-080c6b87953f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=92e84ceb-fbfd-47ab-be52-080c6b87953f; Ip=[192.176.1.74]; Helo=[oa.msg.ericsson.com] X-MS-Exchange-CrossTenant-AuthSource: DU2PEPF0001E9C6.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR07MB7560 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Replace keeping PRNG state in a RTE_MAX_LCORE-sized static array of cache-aligned and RTE_CACHE_GUARDed struct instances with keeping the same state in a more cache-friendly lcore variable. RFC v3: * Remove cache alignment on unregistered threads' rte_rand_state. (Morten Brørup) Signed-off-by: Mattias Rönnblom Acked-by: Morten Brørup --- lib/eal/common/rte_random.c | 30 ++++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/lib/eal/common/rte_random.c b/lib/eal/common/rte_random.c index 7709b8f2c6..adbbf13f0e 100644 --- a/lib/eal/common/rte_random.c +++ b/lib/eal/common/rte_random.c @@ -11,6 +11,7 @@ #include #include #include +#include #include struct rte_rand_state { @@ -19,14 +20,12 @@ struct rte_rand_state { uint64_t z3; uint64_t z4; uint64_t z5; - RTE_CACHE_GUARD; -} __rte_cache_aligned; +}; -/* One instance each for every lcore id-equipped thread, and one - * additional instance to be shared by all others threads (i.e., all - * unregistered non-EAL threads). - */ -static struct rte_rand_state rand_states[RTE_MAX_LCORE + 1]; +RTE_LCORE_VAR_HANDLE(struct rte_rand_state, rand_state); + +/* instance to be shared by all unregistered non-EAL threads */ +static struct rte_rand_state unregistered_rand_state; static uint32_t __rte_rand_lcg32(uint32_t *seed) @@ -85,8 +84,14 @@ rte_srand(uint64_t seed) unsigned int lcore_id; /* add lcore_id to seed to avoid having the same sequence */ - for (lcore_id = 0; lcore_id < RTE_DIM(rand_states); lcore_id++) - __rte_srand_lfsr258(seed + lcore_id, &rand_states[lcore_id]); + for (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) { + struct rte_rand_state *lcore_state = + RTE_LCORE_VAR_LCORE_PTR(lcore_id, rand_state); + + __rte_srand_lfsr258(seed + lcore_id, lcore_state); + } + + __rte_srand_lfsr258(seed + lcore_id, &unregistered_rand_state); } static __rte_always_inline uint64_t @@ -124,11 +129,10 @@ struct rte_rand_state *__rte_rand_get_state(void) idx = rte_lcore_id(); - /* last instance reserved for unregistered non-EAL threads */ if (unlikely(idx == LCORE_ID_ANY)) - idx = RTE_MAX_LCORE; + return &unregistered_rand_state; - return &rand_states[idx]; + return RTE_LCORE_VAR_PTR(rand_state); } uint64_t @@ -228,6 +232,8 @@ RTE_INIT(rte_rand_init) { uint64_t seed; + RTE_LCORE_VAR_ALLOC(rand_state); + seed = __rte_random_initial_seed(); rte_srand(seed);