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Mon, 6 May 2024 04:45:05 -0700 From: Itamar Gozlan To: , , , , , , , Dariusz Sosnowski , Ori Kam , Matan Azrad CC: , Subject: [v2 12/16] net/mlx5/hws: dw order optimization code enhancement Date: Mon, 6 May 2024 14:44:15 +0300 Message-ID: <20240506114419.966498-12-igozlan@nvidia.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240506114419.966498-1-igozlan@nvidia.com> References: <20240314114220.203241-1-igozlan@nvidia.com> <20240506114419.966498-1-igozlan@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D8:EE_|IA1PR12MB6387:EE_ X-MS-Office365-Filtering-Correlation-Id: 71a644f3-4a30-4b87-76e9-08dc6dc1fe91 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230031|82310400017|1800799015|376005|36860700004|921011; X-Microsoft-Antispam-Message-Info: utMYYxVG4xLvvfqKlKgzoCA27jE8HKmzFL0x6DoPZFvwG87g8ONPsEm4gGgB7KKDv5xPL6CHwbivY6fq1tsgWMzx+oE44QPWaJQwNn5B6jiAbseZRVU+XAcGhBDkOnGKcEtV91iolYD/I1jU61CkUGyRlOi1zKxCNXEA3ViSZGcmcrNzkE3hTP/zh2ern1ExgWVOB+mWLw+W40ZvqbQ/y0XOAm3mzkG1hizXeNPWW0s54FLNGRMpvGVXrz5rZkJsctj7a4B4w/XlMtm3pzxCwSZ12iKE18fE9+NbjGfaamMDlxD9GjEWrxSR7L2H57inqkBBDs31p2aiZq4GVKncTouFK65GWH1SIyQVgtev40z3ueeLREN64Ufg/Djk1ByWuDiX3CxvgZHiNtpM3I13xtL2f+eH95iwS0vRnDHx8iFjjd4Br8zK4bvYNZgs19iUvBwX6Zq1X+3VF3WgLAau8iGyiZ1EzmnQe3q4SleovNte+nkFieAQucEDtvyOFeerYcHnXMefwOnI1bzJ4tSMfEY48n5/Zjp8NfPy85UOSWc6gW0FQ8ozAHAV/d7Z9oYCmZv3KnjFnUdeNdUpmA31lkhvFyipNSXykaWmaTt4hbJxEsGm0pFZuBWx4QuyZTm9brZAVFSO/elAi2Yw6fMywTOIzaPzyFlvCRTkND9JXOQ/IFVTcic1rtf7TeLs/EdhhJGeUQFgmDxkNrslEI4oZO7o31WnFqg8AOOR5neQCpGKkZRM8k2a+ZInRarCckBun3r0cQoRSoKyDMKhIYYsP5t2hYZi0s+wzbp1kMvISYH6VX2n3pCYnLw4vYZtMlN5uHtQ7WLlk3ujUAyYCX6XhHI75dow29wLBMKicfb8W7idbLw/SPMGvH5xhGxAv5uG9LHi+Ff9Fqby7tn6pxoHZ+zp5vpR0DpECopy7un0tVgR9f0MXJKrpM/mgjYq1Cuj2RsHJbjWoCh3cLUxrD6tN03IJxwfkWSSYlpOlELo/gqKT2mD9Nfg5JvA6/mlLbAIzmlc61Eatk7lSFc/DNjYQWq87HR8eZ2m8jl7vnMcE0Df+ZFEd5L/1H7YPcAgCuEeDfq0COYiD9ZT1BUJfNDl8Ibg5wJK7G1Ww50ppYnKaes5gSF6d4ajsQZOtAYSh5kucCbjMGA91OgfJHGMrDM23q0eUjAWpLPLqEYTIntvkjd+O+eewkYq+umT076dl5X+nFQkIn3u7fNI/UiI7Agv/Upm4ckXAqoquuY3Tp9sdu0CZcqpdZtEK8Y0bdNSzsNKo118XUlKvd0e2zSgHeHnU1VtFubsLjVI2SgBTNVQdBGqdPLO5VdqyrwY9PASX2p4jgg7eVF59W0+gzI2rHShb2ZbGsJAqN0WeUNtDgcDgy98D6W+cnyQwDftRZ2/gbjF X-Forefront-Antispam-Report: CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230031)(82310400017)(1800799015)(376005)(36860700004)(921011); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 May 2024 11:45:14.5735 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 71a644f3-4a30-4b87-76e9-08dc6dc1fe91 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6387 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Improving code readability by following code styles such as mlx5dr prefix and extracting a support check to an external function call. Also, reducing unneeded static memory allocation using a bounded size macro. Fixes: 88ff41793e7a ("net/mlx5/hws: reorder STE fields to improve hash") Cc: stable@dpdk.org Signed-off-by: Itamar Gozlan Acked-by: Matan Azrad --- drivers/net/mlx5/hws/mlx5dr_definer.c | 39 ++++++++++++++------------- 1 file changed, 20 insertions(+), 19 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index 81d0e0e6df..cffbb7b589 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -31,6 +31,8 @@ #define MLX5DR_DEFINER_QUOTA_BLOCK 0 #define MLX5DR_DEFINER_QUOTA_PASS 2 +#define MLX5DR_DEFINER_MAX_ROW_LOG 32 +#define MLX5DR_DEFINER_HL_OPT_MAX 2 /* Setter function based on bit offset and mask, for 32bit DW*/ #define _DR_SET_32(p, v, byte_off, bit_off, mask) \ @@ -104,21 +106,13 @@ __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ __mlx5_mask(typ, fld)) -#define MAX_ROW_LOG 31 - -enum header_layout { - MLX5DR_HL_IPV4_SRC = 64, - MLX5DR_HL_IPV4_DST = 65, - MAX_HL_PRIO, -}; - /* Each row (i) indicates a different matcher size, and each column (j) * represents {DW5, DW4, DW3, DW2, DW1, DW0}. - * For values 0,..,2^i, and j (DW) 0,..,5: optimal_dist_dw[i][j] is 1 if the + * For values 0,..,2^i, and j (DW) 0,..,5: mlx5dr_optimal_dist_dw[i][j] is 1 if the * number of different hash results on these values equals 2^i, meaning this * DW hash distribution is complete. */ -int optimal_dist_dw[MAX_ROW_LOG][DW_SELECTORS_MATCH] = { +int mlx5dr_optimal_dist_dw[MLX5DR_DEFINER_MAX_ROW_LOG][DW_SELECTORS_MATCH] = { {1, 1, 1, 1, 1, 1}, {0, 1, 1, 0, 1, 0}, {0, 1, 1, 0, 1, 0}, {1, 0, 1, 0, 1, 0}, {0, 0, 0, 1, 1, 0}, {0, 1, 1, 0, 1, 0}, {0, 0, 0, 0, 1, 0}, {0, 1, 1, 0, 1, 0}, {0, 0, 0, 0, 0, 0}, @@ -3471,16 +3465,16 @@ mlx5dr_definer_find_best_range_fit(struct mlx5dr_definer *definer, static void mlx5dr_definer_optimize_order(struct mlx5dr_definer *definer, int num_log) { - uint8_t hl_prio[MAX_HL_PRIO - 1] = {MLX5DR_HL_IPV4_SRC, - MLX5DR_HL_IPV4_DST, - MAX_HL_PRIO}; + uint8_t hl_prio[MLX5DR_DEFINER_HL_OPT_MAX]; int dw = 0, i = 0, j; int *dw_flag; uint8_t tmp; - dw_flag = optimal_dist_dw[num_log]; + dw_flag = mlx5dr_optimal_dist_dw[num_log]; + hl_prio[0] = __mlx5_dw_off(definer_hl, ipv4_src_dest_outer.source_address); + hl_prio[1] = __mlx5_dw_off(definer_hl, ipv4_src_dest_outer.destination_address); - while (hl_prio[i] != MAX_HL_PRIO) { + while (i < MLX5DR_DEFINER_HL_OPT_MAX) { j = 0; /* Finding a candidate to improve its hash distribution */ while (j < DW_SELECTORS_MATCH && (hl_prio[i] != definer->dw_selector[j])) @@ -3632,6 +3626,16 @@ int mlx5dr_definer_compare(struct mlx5dr_definer *definer_a, return 0; } +static int +mlx5dr_definer_optimize_order_supported(struct mlx5dr_definer *match_definer, + struct mlx5dr_matcher *matcher) +{ + return !mlx5dr_definer_is_jumbo(match_definer) && + !mlx5dr_matcher_req_fw_wqe(matcher) && + !mlx5dr_matcher_is_resizable(matcher) && + !mlx5dr_matcher_is_insert_by_idx(matcher); +} + static int mlx5dr_definer_calc_layout(struct mlx5dr_matcher *matcher, struct mlx5dr_definer *match_definer, @@ -3693,10 +3697,7 @@ mlx5dr_definer_calc_layout(struct mlx5dr_matcher *matcher, goto free_fc; } - if (!mlx5dr_definer_is_jumbo(match_definer) && - !mlx5dr_matcher_req_fw_wqe(matcher) && - !mlx5dr_matcher_is_resizable(matcher) && - !mlx5dr_matcher_is_insert_by_idx(matcher)) + if (mlx5dr_definer_optimize_order_supported(match_definer, matcher)) mlx5dr_definer_optimize_order(match_definer, matcher->attr.rule.num_log); /* Find the range definer layout for match templates fcrs */